[SI-LIST] Re: DDR propagation delay and packaging
- From: Perry Qu <perry.qu@xxxxxxxxxxx>
- To: Bradley S Henson <bhenson@xxxxxxxxxxxx>
- Date: Tue, 02 Dec 2003 09:06:38 -0500
Bradley, Brian:
Thanks for your comments. I understand the importance of simulating packaging
effect. The dilemma is where
we measure propagation delay. This happened to any IC with electrically long
packaging, but particularly
important for DDR due to tight margin. In many situation, the
shelf/ledge/glitch at package pin waveform
will exaggerate the difference between min/max delay.
If IC vendor refused to give timing spec on chip pad, what's the best
compromise in this case ?
Regards
Perry
Bradley S Henson wrote:
> We simulate DDR from/to the ASIC pad. Packaging effects including waveform
> settling (Zo, xtalk etc) as well as delay and especially skew, are critical
> to getting a robust timing interface with DDR. Whether you are simulating
> to create a timing budget or to verify one, packaging effects need to be
> considered.
>
> Brad Henson
> Raytheon Space and Airborne Systems
>
>
> Perry Qu
> <perry.qu@alcatel To: si-list
> <si-list@xxxxxxxxxxxxx>
> .com> cc:
> Sent by: Subject: [SI-LIST] DDR
> propagation delay and packaging
> si-list-bounce@fr
> eelists.org
>
>
> 12/01/2003 01:39
> PM
> Please respond to
> perry.qu
>
>
>
> Hi, everyone:
>
> I'm doing SI work on a 200 MHz DDR interface. To measure propagation, we
> used the traditional method, i.e., simulate driver with reference load
> and simulate driver with real load. Measure time difference from Vmeas
> at reference load to Vref (+/- certain noise) at receiver.
>
> Now the question I had: the controller is a big ASIC with maximum delay
> on packaging itself around 140 ps. Since all timing are defined at pin,
> I have to use the waveform at pin to measure delay. In the case of
> memory write to controller, waveform at pin can get distorted due to
> packaging. I get shelf/ledge on the edge. I use the following two
> approach to measure delay and get very different results (more than
> 100ps):
>
> 1. use waveform at packaging pin to measure delay;
> 2. use waveform at chip pad to measure delay and substracted the ASIC
> packaging delay to get the delay at pin;
>
> ASIC vendor suggest approach 1 but I don't feel quite comfortable.
> Wonder how all you experts are dealing with this issue ?
>
> Thanks
>
> Perry
>
> --
> Perry Qu
>
> Design & Qualification | 600 March Road
> Alcatel Canada | Ottawa, ON K2K 2E6, Canada
>
> DID: (613) 7846720 | FAX: (613) 5993642
>
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--
Perry Qu
Design & Qualification | 600 March Road
Alcatel Canada | Ottawa, ON K2K 2E6, Canada
DID: (613) 7846720 | FAX: (613) 5993642
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