[SI-LIST] Re: DDR point to point termination
- From: "Chris McGrath" <chris.mcgrath@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 Jul 2004 12:04:23 -0700
Two issues that we have run into with point-to-point SSTL2 DDR SDRAM
implimenations are:
1. Increased EMI (faster switching due to wider voltage swing).
2. More variance in signal-to-signal timing due to routing,
manufacturing, or environmental tolerances.
While #1 is more universal, #2 is something that we didn't really
consider until after we had a number of units in the lab with a fairly
wide range in the amount of timing margins. I think we saw something
like a 30% variation in the amount of margin we had in our timing. We
did manage to correlate this to simulations (min-typ-max) and it mainly
had to do with the same change in slew rates that had negative effects
for EMI.
I should add that we had longer traces (~7") and had series terminators
on both sides of the net. Adding parallel termination produced a much
more repeatable timing margin.
-Chris
> -----Original Message-----
> From: Peterson, James F (FL51)=20
> [mailto:james.f.peterson@xxxxxxxxxxxxx]=20
> Sent: Tuesday, July 13, 2004 1:20 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR point to point termination
>=20
>=20
> maybe it's 4 devices because of data width not depth...
>=20
> I am also interested in DDR SSTL term schemes. I am=20
> simulating a point to point architecture with no pull-ups in=20
> the interface. I am assuming a longer run than 2 inches. More=20
> like 6 inches. the data bus is bi-directional so i have a=20
> series terminating resistor at both drivers. This seems to be=20
> very effective. The recommended pull-up adds no benefit, and=20
> adds to the power so I don't plan on using it. The catch,=20
> though, is to make sure the bus doesn't tri-state, cause=20
> it'll float w/o the pull-up.
>=20
> jim peterson
> honeywell
>=20
> -----Original Message-----
> From: Landrum, Chris [mailto:chris_landrum@xxxxxxxxxx]
> Sent: Tuesday, July 13, 2004 1:02 PM
> To: arich1970@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR point to point termination
>=20
>=20
>=20
> I have implemented a point to point DDR interface (200MHz)=20
> using series resistors located in the middle of the data=20
> traces. I have seen the same app note you speak of requiring=20
> the trace lengths to be less than 2in, which seems to work=20
> well in my application. =3D20
>=20
> However, you describe a DDR interface consisting of 4=20
> devices. This is not point-to-point as the devices will=20
> share data lines. This interface should be simulated.
>=20
>=20
>=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Aric Hadav
> Sent: Tuesday, July 13, 2004 11:24 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR point to point termination
>=20
> Hi,
>=20
> I'm designing an embedded system with DDR. I'm using a CPU=20
> connected to an=3D20 on board four 16 bit DDR devices (no=20
> DIMM). I have 2 questions though - 1. can I use only a series=20
> termination on the data bus (I saw a few AN that=3D20 state=20
> that if the disctance between the controller and the DDR IC's=20
> is upto=3D20 2" its ok). has anyone did it with a 200MHz clock=20
> ? 2. since the address and control lines operate in half the=20
> data rate and the=3D20 DDR controller is very lightly loaded=20
> (only 4 chips) can I use only series=3D20 termination for=20
> address and control ? has anyone did it with good resaults ?
>=20
> thanks,
>=20
> Aric
>=20
> _________________________________________________________________
> Add photos to your messages with MSN 8. Get 2 months=20
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