[SI-LIST] Re: DDR point to point termination
- From: "Gil Gafni" <gil.gafni@xxxxxxxx>
- To: <arich1970@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 Jul 2004 10:03:26 -0700
Hello Aric et all
We designed a DDR 166MHz (it has about the same rise time as the
200MHz...) and up to 6 components, traces are about 2". The key for our
design was LOW LOW COST, so any passive that we can eliminate is a major
contribution, in particular if you have a wide data and/or address bus.
Typically a DDR interface can get to about 80 - 100 signals, so any
resistor taken out...
What did we do:
1. We made sure that all critical signals will have excllent routing,
i.e. no more than two vias, and an adjacent GND plane for the best
return path (bear in mind a 6 layers design...) I do not know if you
have any constrain for layer count, if you do not, make sure ALL the
signals are routed in the best layout layers that you have.
2. For the Data we have used only pull ups (to Vtt it is an SSTL...),
placed at the middle, no other passive was added
3. For the Address and control we initially placed a series terminations
and pull ups at the split point, we ended up having only the series
termination.
You did not mention, but I ASSUME that it is SSTL interface. If I am
right, then it makes sense for you to use the same scheme, the idea is
that for reflection wise, neither the data (being bi-directional) nor
the address and control (being uni-directional but loaded) need any
terminations. Reflections to some extent WILL OCCUR, but if you simulate
and see that you can "live with them" i.e. the overshoots and
undershoots are not "killing" your buffers, then you are ok. We
simulated , and we got a "decent" eye pattern for the data, and we
designed the strobes to meet that. As for the address it was even
better. SSTL gives you a narrow window of opportunity on one end, but
better noise immunity.
At the end of the day, although classic SI tells us that we need to
eliminate reflections, we only want to meet timing (i.e. setup and
hold) on both ends of the interface.
Hope this information helped
Best of luck
Gil
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Aric Hadav
Sent: Tuesday, July 13, 2004 8:24 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR point to point termination
Hi,
I'm designing an embedded system with DDR. I'm using a CPU connected to
an
on board four 16 bit DDR devices (no DIMM).
I have 2 questions though -
1. can I use only a series termination on the data bus (I saw a few AN
that
state that if the disctance between the controller and the DDR IC's is
upto
2" its ok). has anyone did it with a 200MHz clock ?
2. since the address and control lines operate in half the data rate and
the
DDR controller is very lightly loaded (only 4 chips) can I use only
series
termination for address and control ? has anyone did it with good
resaults ?
thanks,
Aric
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