[SI-LIST] Re: DDR logic threshold
- From: "Fraiman, Edi" <Edi.Fraiman@xxxxxxxxxx>
- To: <naren.thesia@xxxxxxxxx>, "SI-List" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 21 Aug 2006 10:08:56 -0400
Hi,
Find below explanation from SSTL_2 JEDE STANDARD
The ac values are chosen to indicate the levels at which the receiver
must meet its timing specifications.
The dc values are chosen such that the final logic state is
unambiguously defined, that is once the receiver input has
crossed this value, the receiver will change to and maintain the new
logic state. The reason for
this approach is that many input wave-forms will include a certain
amount of "ringing". The
system designer can be sure that the device will switch state a certain
amount of time after the
input has crossed ac threshold and not switch back as long as the input
stays beyond the dc
threshold.
Best regards,
Edi Fraiman
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Naren Thesia
> Sent: Monday, August 21, 2006 12:59 AM
> To: SI-List
> Subject: [SI-LIST] DDR logic threshold
>
>
> Hi,
> I unable to get exact logic behind "to define AC & DC
> threshold for DDR".
>
> Any one has any clue?
>
> Regards,
> Naren
>
>
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