[SI-LIST] Re: DDR DRAM
- From: "Landrum, Chris" <chris_landrum@xxxxxxxxxx>
- To: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- Date: Thu, 29 Jul 2004 11:27:03 -0400
Scott, thanks for the response...
I am currently working on a design where I have a point to point DDR
implementation using one DDR DRAM component. There is a single
terminator in series approx at the mid-point of the line. I have done
simulations in Spectraquest and the worst case crosstalk is around
100mV. Spectraquest does not seem to show how this 100mV translates
into jitter on the victim trace though, at least I don't think crosstalk
is considered in the reflection simulations of Spectraquest. Anyone
know if it does?
As for voltage margins, I have done a quick calculation and it appears
to me that the noise margin is on the order of 300mV for the interface.
This assumed 2.6 VDDQ (DDR400), 1.9V VOH(min), 0.69V VOL(max), 1.6V
VIH(min), 0.99V VIL(max).
Subtracting out the 100mV of simulated crosstalk, 75mV of power supply
ripple, and 25mV or so for things unaccounted for, it seems there is
still 100mV of noise margin. This seems pretty manageable. Did I forget
something?
With 100mV of noise margin after having considered the sources, I don't
foresee that mis-clocking will be a problem. So it sounds like, my
biggest issue for this design is the jitter effects on the timing
budget....
Thanks.
-----Original Message-----
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]=20
Sent: Thursday, July 29, 2004 10:52 AM
To: Landrum, Chris
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] DDR DRAM
Chris,
No, your thinking is not sound. The margins on DDR busses are generally
low and require careful consideration of in-bus crosstalk. Crosstalk=20
within a bus on the data lines can be looked at in two ways.
#1) Crosstalk can be seen as noise injected from one signal into=20
another. This noise then adds to the instantaneous voltage on the=20
victim signal. This upset can look like additional positive or negative
overshoot, it can look like IEEE undershoot, in that it it supresses the
rising edge transition, or it can cause jitter in the waveform. All of=20
these can be detremental on bus operation. First, jitter translates=20
into a reduction of timing margin. Second, excessive overshoot can=20
cause receiver voltage to extend beyond the maximum operating range of=20
the device. This overshoot operation can cause eventual distruction of=20
the input through electromigration.
#2) Crosstalk can be seen as a dynamic impedance and propagation=20
velocity change on the victim line. This dynamic change, the magnitude=20
is dependent upon the magnitude of the crosstalk, and also commonly=20
called the even and odd model coupled transmission line characteristics,
is another way of looking at why excess jitter, overshoot and IEEE=20
undershoot occur in coupled transmission lines. Again, this can be=20
extreme enough to break bus operating margins for both voltage and
timing.
Finally, crosstalk from DQ to QDS lines can be catestrophic, since noise
injected can rise to the extreme of causing false strobe transitions at=20
the receivers. Early DDR chipsets had to be redesigned due to DQ=20
signals being routed adjacent to DQS signals inside of packages, causing
bus failures.
I hope this description helps you.
regards,
scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
(503) 750-6481 Cellular
http://www.teraspeed.com
Teraspeed is the registered service mark of=20
Teraspeed Consulting Group LLC
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