[SI-LIST] Re: DDR DRAM

  • From: Kevin Normoyle <Kevin.Normoyle@xxxxxxx>
  • To: si-list@xxxxxxxxxxxxx, ajmani@xxxxxxxxxx
  • Date: Tue, 7 May 2002 11:41:07 -0700 (PDT)

I think you need to show the timing analysis for sampling
read data.

Micron has a very good app note that highlights different ways
of adding up the numbers.

You mention that both DRAMs meet the jedec spec but your part
doesn't work. 

It sounds like you don't have the right delay line in your asic
to align the data and strobe appropriately, so that you can sample
correctly, given the jedec-spec'ed variances and variances in your
board layout.

Before you can decide what you need to do to make your current
thing "better"...you need to figure out the full read timing analysis,
I think.

For instance, if your design can tolerate extra read return latency,
it may be that you need to lengthen the data strobes on your board,
relative to the data.

Without seeing the numbers, it's hard to say where you have margin
to play with. It's possible that your design doesn't have enough
skew tolerance inside the asic, so that you might not be able
to work for all corner cases, unless you make more drastic asic changes.

I may be off base. Apologies if so.

-kevin

> Delivered-To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR DRAM
> To: si-list@xxxxxxxxxxxxx
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> 
> Hello SI-LISTers,
> Thanks to all of you who replied to my post.  A number of questions have
> been raised and I wish to answer them.
> 
> 1) I used HP 2.5 GHz probes with HP Infinium 1.5 GHz oscilloscope, using 8
> GHz sampling rate.
> 
> 2) I had gone through several Application Notes/other material and decided
> to use source terminations because of the following constraints:
> 
>    a) I do not have enough board space to provide parallel terminations or
> both.
> 
>    b) I am already exceeding our power budget, and can't afford the
> additional current drain of parallel terminations.
> 
>    c) The parallel termination used by me (on the failing bits only) were
> selected by simulations and were also found to work on the actual card.
> 
> The problem as I see is that brand "X" DRAM puts data after the Strobe
> (although still within their specs of 500 ps), whereas brand "Y" DRAM puts
> data before the Strobe.  Hence, I have a problem of matching my card layout
> to work with both DRAMs.
> 
> Regards, Ravinder
> PCB Development and Design Department
> IBM Corporation
> Email: ajmani@xxxxxxxxxx
> ***************************************************************************
> Always do right.  This will gratify some people and astonish the rest.
> .... Mark Twain
> 
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