[SI-LIST] Re: DDR DRAM
- From: "Chris McGrath" <chris.mcgrath@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 2 Aug 2004 10:14:28 -0700
I just noticed this from Brian's email:
"we will often recommend for example 2H spacing from DQ to DQS, 3H
spacing from DQ to DQS, and 4H to 5H spacing around clocks"
Did you mean 3H from DQ to addr/control?
Thanks,
Chris
> -----Original Message-----
> From: Jim Antonellis [mailto:janton@xxxxxxxxxxxxxxxxxxxxxx]=20
> Sent: Monday, August 02, 2004 1:00 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR DRAM
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> Brian, Chris, Scott,
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> Thanks for your insight on this topic. Funny how timely some
> of these posts are.... I had just finished building my 5-line=20
> coupled models to start my DDR2 xtalk analysis and help firm=20
> up my budgets when I read this email!
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> I'd appreciate any insight you have on the data patterns=20
> required to perform the xtalk and ISI analysis on DDR (which=20
> might be the general case for any non-encoded data stream?)?=3D20
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> Thx,
> Jim
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> -
> Jim Antonellis jim.antonellis@xxxxxxxxxxxxx
> Sandburst Corp www.sandburst.com
> Office: 978.689.1669=3D20
> Cell: 978.618.4745
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> This message and any attachments are Confidential and may be=20
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> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Moran, Brian P
> Sent: Thursday, July 29, 2004 11:39 AM
> To: chris_landrum@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR DRAM
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> Hi Chris,
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> Actually x-talk control strategy is a critical aspect of the=20
> DDR interface. There are both SI issues as well as timing=20
> issues in designs where x-talk is not properly controlled.=20
> You really need to use 3 or 4 line fully coupled tline models=20
> in all simulations, as well as stimulus and aggressor=20
> patterns that will identify worst case even and odd mode, as=20
> well as ISI effects. The margins nowadays are not that=20
> generous, so you really need to=3D3D20 develop an efficient=20
> strategy. With dual channel platforms it becomes even more=20
> of a challenge. =3D3D20
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> As Scott elluded to, it is usually wise to define your=3D3D20=20
> motherboard routing rules so as to provide additional spacing=20
> around clocks and strobes. If you look at a typical Intel=20
> design guide we will often recommend for example 2H spacing=20
> from DQ to DQS, 3H spacing from DQ to DQS, and 4H to 5H=20
> spacing around clocks. A similar strategy should be adhered=20
> to in the package. Providing additional spacing around clocks=20
> and strobes is an efficient use of routing space since there=20
> are relatively few of them. If you limit your xtalk to within=20
> the DQ or ADDR bus and keep your clocks annd strobes clean=20
> you will find much more solution space than if you simply use=20
> a single spacing rule across the interface. =3D3D20
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> Brian P. Moran=3D3D20
> Senior SIE Engineer=3D3D20
> Intel Corporation=3D3D20
> brian.p.moran@xxxxxxxxx=3D3D20
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> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Landrum, Chris
> Sent: Thursday, July 29, 2004 7:33 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR DRAM
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> I apologize for what might be a simple question...
> =3D3D20
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> Assuming no other interfaces are in close proximity to a DDR=20
> DRAM databus, is it true that one does not have to worry=20
> about crosstalk between the data bits (or other DRAM signals=20
> for that matter)? Let's say the traces are only 4 inches=20
> long on a PCB. And assume the case when a write is=20
> occurring. Since, the controller is not receiving at the=20
> time, is it safe to assume that whatever crosstalk=20
> interference there may be will "settle-out" by the time the=20
> DQS strobes the data in?
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> =3D3D20
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> It seems to me that the real worry is only crosstalk from=20
> interfaces not related to the DRAM bus, that could be=20
> potentially be switching at the same time the data is=20
> latching into the DRAM.
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> =3D3D20
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> Is this thinking sound?
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> =3D3D20
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> -Chris
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