[SI-LIST] Re: DC power Analysis/Current Density
- From: "Brad Brim" <bradb@xxxxxxxxxxx>
- To: <balaseven@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 12 Apr 2012 09:22:35 -0700
hi Bala,
As Patrick Carrier mentioned, there are IPC guidelines for current carrying
limits but beyond these you need to perform a thermal simulation to get the
detailed information you desire. If you are using PowerDC you already have
such capability available. In addition to the more familiar DC IR Drop
analysis PowerDC also performs electrical/thermal cosimulation. This is not
just a thermal analysis done after the current distributions are computed
but it solves the nonlinear problem of temperature-dependent electrical
properties of materials and provides more accuracy for both the electrical
and thermal analyses.
Jim Antonellis mentioned three concerns you can judge with more confidence
after you have performed an electrical/thermal cosimulation to get accurate
results for both current flow and temperature distribution. However, your
original inquiry cited a much more simple design task. I interpret your
design constraint as a maximum local temperature of 70 degrees allowed for a
power plane. You can easily assure this temperature spec is met through
electrical/thermal cosimulation by examining the temperature distribution of
the plane(s) of interest. You can look at fancy color-shaded graphics or
simply set a temperature constraint and let the software warn you if that
constraint is violated.
best regards,
-Brad Brim
Sigrity
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of bala
> Sent: Thursday, April 12, 2012 7:38 AM
> To: Reams, Bill; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DC power Analysis/Current Density
>
> Hi Reams
> Yes,Thanks for your detailed explanation.We usually taken
> care all these theoretical data,but when we use some tool
> like Sigrity PowerDC or sentinePSI,It shows some map with
> different color and 'current density'.How can we conclude
> whether a particular Density value is dangerous or safe.Is it
> tool specific?certainly not.For example if the current
> density map shows
> 2.5e5 Amps/mmsquare.Does this safe margin?Thanks for your time.
>
> Regards
> bala
>
> On Thu, Apr 12, 2012 at 7:55 PM, Reams, Bill
> <bill.reams@xxxxxx> wrote:
>
> > Bala,
> >
> > SHORT ANSWER:
> > For "small" currents like your example, there are standards such as
> > those published by IPC that can be used. Or for a quick calculation
> > that is good enough for the 99% of the time when we're designing
> > something that's not life critical, there are on line width
> > calculators available - just type something like "PCB current trace
> > calculator" (or "wire ampacity calculator" if you're designing a
> > wiring harness) in your favorite search engine. By trying different
> > numbers, you'll find out why for example the
> > 100+A CPU currents get routed on one or more planes (planes
> are really
> > 100+just
> > very wide traces). And with that said, when we're dealing
> with extreme
> > currents, high voltages, life critical systems, etc much
> more care and
> > understanding of the issues should be taken than trusting on line
> > calculators or industry standards (call in an expert if needed).
> >
> > MORE DETAILED ANSWER:
> > Until you reach "extreme" currents and/or voltages, the
> current limit
> > is really set by two things: the resistive heating and the
> voltage drop.
> >
> > Narrow traces have a higher resistance than wide traces and
> therefore
> > will experience more heating from a given current flow.
> Why, one form
> > of Ohm's Law gives use P=I^2*R. The trace has "R", you're
> sending "I"
> > down the trace and "P" is the energy that gets converted to
> heat. If
> > you have an upper limit on your ambient temperature and a
> limit on how
> > close you're willing to let the trace get to melting the board
> > dielectric, you have a maximum allowed temperature rise
> from resistive
> > heating (Trise = Tlimit - Tambient) that's say 50-80C
> depending on your board material and max allowed ambient.
> > Personally I'm going to be a bit more conservative in my
> designs than
> > going to just short of the melting point; typically I'll limit the
> > temp rise to something like <10-20C but that's a design decision
> > you'll make. So for the example you give, I might use an
> 8mil trace on
> > an external layer or 20mils on an internal layer from a
> heating standpoint.
> >
> > Similarly, long traces have more resistance than short
> traces of the
> > same width. Thus for a given current, the voltage drop
> along the trace
> > will be more for the long trace than the short trace (again, just
> > Ohm's law). If the voltage drops to much, the circuit at
> the end may
> > not be supplied with a high enough voltage to operate
> correctly. Take
> > the above 8/20mil traces as an example. If the traces are 10 inches
> > long, the 20mil trace causes ~170mV of drop which is
> probably okay for
> > a 3.3V IC. But the 8mil trace would cause >400mV of loss
> which would
> > take a normal 3.3V IC below its allowed minimum operating
> voltage (it
> > might work but you'd be out of spec so your product might
> occasionally suffer some seemingly random "issues").
> > In both these cases, for a long trace you might need to widen the
> > trace not for current carrying capacity but to limit the
> voltage drop.
> >
> > Note that the voltage drop is part of the reason that high current
> > regulators for e.g. CPUs have a voltage sense connection
> that is made
> > at the die (or at least on the board right under the CPU).
> That allows
> > the regulator to generate a voltage that is high by the amount of
> > voltage drop between the regulator and the CPU. So remember that if
> > you design a circuit with a regulator that has a voltage sense, you
> > should consider carefully where the voltage sense connects
> on your board.
> >
> >
> > Bill Reams
> > Senior HW Engineer
> > Hewlett-Packard Company
> >
> > +1 512 432 8851 / Tel
> >
> > bill.reams@xxxxxx / Email
> > 14231 Tandem Boulevard
> > Austin, TX 78728
> > USA
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of bala
> > Sent: Thursday, April 12, 2012 7:29 AM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] DC power Analysis/Current Density
> >
> > Hi Experts,
> > I have a question on 'DC power analysis'. Hope the maximum
> allowed IR
> > drop/V-drop value can be concluded from the line/load
> regulation. Is
> > there any general formula to find out a maximum allowed 'current
> > density' for a particular power plane? For example, if I want to
> > simulate 3.3V, 0.8A plane@maximum of 70 degree Celsius, how
> shall we
> > find out the maximum allowed current density for this case?
> >
> > Regards
> >
> > bala
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