[SI-LIST] Re: Current Return Vias
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
- To: "steve weir" <weirsi@xxxxxxxxxx>, <Ken.Cantrell@xxxxxxxxxxxxxxxx>, <Chris.Cheng@xxxxxxxxxxxx>, "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 26 Jul 2006 10:09:39 -0600
Steve -
I never said or implied that arbitrarily traversing any cavity with any
combination of signals without concern for the Z-axis return path was
acceptable. I do agree about the silly extreme.
Ken
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Wednesday, July 26, 2006 9:47 AM
To: Ken.Cantrell@xxxxxxxxxxxxxxxx; Chris.Cheng@xxxxxxxxxxxx; Ken
Cantrell; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Current Return Vias
Ken, I disagree. I think that Chris' examples graphically
demonstrate the fact that we cannot arbitrarily traverse any cavity
with any combination of signals without concern for the Z axis return
path and yield desired results. I find it very much in context with
the original discussion of the what is for many cases at current
signaling edge rates an equally silly extreme in the form of an
individual return stitch via per signal via.
Regards,
Steve.
At 07:32 AM 7/26/2006, Ken Cantrell wrote:
>Chris -
>That was my point, the example was extreme and didn't address the issue.
>Ken
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
>Sent: Tuesday, July 25, 2006 6:05 PM
>To: Ken Cantrell; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Current Return Vias
>
>
>How stupid it is for the design below vs. statements like "all you need =
>is the power/ground plane and decoupling capacitance for the return =
>current path, no vias needed". Wait, aren't they the same stupid concept =
>?
>While the example is extremely, I have been called to fix package =
>designs (not my own) that conveniently forgot to provide return vias =
>between upper and lower power/gnd planes because package designers want =
>to steal those large core via locations for their signal escapes to =
>bottom layers. If you read Larry's reply carefully, you will see similar =
>experiences he refers to. Some highspeed signals experience a huge =
>glitch everytime some slow JTAG signals toggles hundreds of mils away on =
>a package. As it turns out, the package designer forgot to provide the =
>through vias for the reference planes and the return current decided to =
>take the nearest return via as return path which is on the highspeed =
>signal area hundreds of mils away.
>At the end, talk is cheap. If you truly believe return via is useless =
>and plane and decoupling capacitance is good enough, why border to drill =
>those vias on packages. Put your money where your mouth is. And if you =
>are too chicken to do so, you are not practicing what you preach.
>
>-----Original Message-----
>From: Ken Cantrell [mailto:Ken.Cantrell@xxxxxxxxxxxxxxxx]
>Sent: Tuesday, July 25, 2006 6:49 AM
>To: Chris Cheng; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: Current Return Vias
>
>
>Chris,
>Nobody said it was OK to do stupid stuff.
>Ken
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
>Sent: Monday, July 24, 2006 5:15 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Current Return Vias
>
>
>Ok, I'll give you an evidence if you dare to take it up and try on your =
>=3D
>clients design and see if you can keep your job after that.
>
>In a typical multi-layer BGA design, the signal fan out is almost =3D
>entirely done on the top half of the package and reference to the planes =
>=3D
>on top. The power and ground planes are connected through blind and =3D
>buried vias through the package to the PCB. As such a package design can =
>=3D
>therefore stop the via connection at any plane he/she desire.
>
>My challenge to you is just connnect all those power/ground pin on the =
>=3D
>peripheral (not directly underneath the die) to the bottom half of the =
>=3D
>package only and not to the top half where the signals are reference to. =
>=3D
>Let's see how much ground/power bounce you will observe.
>
>BTDT, have you ?
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Lee Ritchey
>Sent: Monday, July 24, 2006 3:46 PM
>To: Ken Cantrell; kenny_frohlich@xxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Current Return Vias
>
>
>Ken,
>
>Well put. When someone makes the statement that ground vias are =3D
>required
>to provide a path for return currents, it needs to be accompanied with =
>=3D
>some
>evidence.
>
>
> > [Original Message]
> > From: Ken Cantrell <Ken.Cantrell@xxxxxxxxxxxxxxxx>
> > To: <kenny_frohlich@xxxxxxxxx>; <leeritchey@xxxxxxxxxxxxx>;
><si-list@xxxxxxxxxxxxx>
> > Date: 7/24/2006 6:51:24 AM
> > Subject: [SI-LIST] Re: Current Return Vias
> >
> > Kenny,
> > At 133MHz, and assuming your edge rates are > 500ps, you aren't going =
>=3D
>to
> > need them, even if you have twice as many layers. It's an important
>effect,
> > but at 133MHz it's not relevant. What is important, as Lee indicated, =
>=3D
>is
> > your PDS design.
> >
> > Ken
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Kenny Frohlich
> > Sent: Saturday, July 22, 2006 1:56 PM
> > To: leeritchey@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Current Return Vias
> >
> >
> > Lee,
> > I'm not talking about jumping from one layer to the next adjacent =
>=3D
>layer
> > which shares the same referrence plane. In this case, I do not need a
> > ground via. But I'm asking about jumping from one layer to another =
>=3D
>layer
> > that has a differrent reference ground plane. For example, on an 8 =
>=3D
>layer
> > PCB stackup where the two ground planes are layers 2 and 7, the =3D
>signal
> > jumps from the top layer (layer 1) to the bottom layer (layer 8).
> >
> > Thank you
> > Kenny
> > Lee Ritchey <leeritchey@xxxxxxxxxxxxx> wrote:
> > Kenny,
> >
> > It is not true that you need a "return current" via next to each layer
> > changing signal via. I continue to be amazed that engineers who are
> > looked upon as SI experts say such things.
> >
> > Imagine you have a 4 layer PCB, such as the mother board in a PC, =3D
>where
> > there are only two planes, one Vdd and one ground, where would such =
>=3D
>vias
> > connect? There have been billions of these made to date that work just
> > fine and have very fast signals on them. The return currents you are
> > concerned about find their way from plane to plane through the =3D
>collection
> > of decoupling capacitors and interplane capacitance that you had to
> > engineer into the power delivery system in order to make it stable. =
>=3D
>Focus
> > on this and the return currents take care of themselves. EMI is =3D
>minimized
> > he same way..
> >
> >
> >
> >
> > > [Original Message]
> > > From: Kenny Frohlich
> > > To:
> > > Date: 7/22/2006 6:45:56 AM
> > > Subject: [SI-LIST] Current Return Vias
> > >
> > > Dear Experts,
> > > I understand that I need to provide ground vias next to via =3D
>explictly
> > for the purpose of letting return currents jump between layers. I know
> > it's a requirement for high speed signals, especially differrential
> > signals. Is this also required for low speed single-ended signals =3D
>(133Mhz
> > or slower)?
> > > If this is a requirement, what would be a good signal via to ground =
>=3D
>via
> > ratio? For example, there are five signal vias within a 1 inch area, =
>=3D
>how
> > many ground vias do I need?
> > >
> > > Thank you
> > > Kenny
>
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