[SI-LIST] Re: Current Return Vias

  • From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
  • To: "Steve Weir" <weirsi@xxxxxxxxxx>, "Ihsan Erdin" <erdinih@xxxxxxxxx>, giovanni.guasti@xxxxxxxxxx
  • Date: Tue, 25 Jul 2006 08:39:08 -0700

Steve,

Complex answer, but good.  Problem with this answer is it confuses me.  At
what frequencies does an engineer have to do the special via treatment? 
I'm sure it is above where most logic operates and is likely around 10GE
launches, etc.


> [Original Message]
> From: steve weir <weirsi@xxxxxxxxxx>
> To: <leeritchey@xxxxxxxxxxxxx>; Ihsan Erdin <erdinih@xxxxxxxxx>;
<giovanni.guasti@xxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 7/24/2006 10:05:43 PM
> Subject: [SI-LIST] Re: Current Return Vias
>
> Lee, et-al I agree that there is a good deal of misinformation that 
> circulates on this subject.  It is another topic that ultimately 
> comes down to the numbers.  Single stitch vias are incapable of 
> "maintaining return path continuity".   What they can do is act in 
> concert with other vias and planes, so that the net scattering has 
> acceptably low loss.
>
>  From my experience path impedance continuity to high frequencies as 
> determined by low, linear S21 loss, and good S11 loss requires a 
> pattern of vias associated with each launch. Teraspeed designs such 
> launches everyday.  But a return via pattern on a signal by signal 
> basis eats up expensive real estate far too quickly to be practical 
> for managing routing layer transitions.
>
> Usually we see these circumstances / effects from stitch vias:
>
> For boards without either multiple Vss layers, or puddles, there is 
> nothing to stitch.  It is down to bypass caps.
>
> For boards with multiple Vss layers and modest edge rates, the Vss 
> vias of the bypass capacitors and components are usually well within 
> the quasi static extents.  Additional stitch vias directed at 
> individual signals have very little impact. If for some reason a PCB 
> has a lot of open real-estate, ( more often test vehicles than real 
> PCBs ) then the situation changes and distributing stitch vias 
> provides quantifiable benefits.  For most practical designs the 
> density and distribution is usually OK without adding extra stitch 
> vias.  When in doubt, do the homework.
>
> For boards with very fast edge rates, the quasi static extents are 
> small, and stitch vias associated with individual signals display 
> more pronounced effects.  But, the dimensions become such that we 
> really have to throw away the quasi static model and look at the 
> various wave modes.  This requires a 3D full wave tool like HFSS, or 
> CST.  For really fast signals, I reiterate that I cannot think of a 
> case where one stitch via associated with one signal could make the 
> difference between acceptable and unacceptable S parameter 
> results.  Either a pattern of vias is needed to make the difference, 
> ( sic launch ) or none at all.
>
> Regards,
>
>
> Steve.
>
> At 03:34 PM 7/24/2006, Lee Ritchey wrote:
> >Ihsan,
> >
> >Well put.
> >
> >
> > > [Original Message]
> > > From: Ihsan Erdin <erdinih@xxxxxxxxx>
> > > To: <giovanni.guasti@xxxxxxxxxx>
> > > Cc: <si-list@xxxxxxxxxxxxx>
> > > Date: 7/23/2006 7:36:40 AM
> > > Subject: [SI-LIST] Re: Current Return Vias
> > >
> > > Giovanni,
> > > The EMC justification of a ground via in the close proximity of a
> >switching
> > > via is to minimize radial waves to the edges of the card by providing
a
> > > "return path" (I hate this phrase...) A two-wire kind of transmission
line
> > > -as you put it- would be another rationalization against the impedance
> > > discontinuity for high-speed signals. In practice, however, the
placement
> >of
> > > a ground via close enough to a switching via in order to provide a
> >matching
> > > impedance to -say 50 ohm- or to mitigate radial wave propagation is in
> >most
> > > cases -if not all- physically impossible. I think this kind of SI/EMI
> > > rule-of-thumbs are based on a qualitative understanding of
electromagnetic
> > > theory rather than rigorous research results. In this context, I share
> >Lee's
> > > stance to debunk these recommendations because they have significant
> >effect
> > > on the design cost by closing routing channels and eating up on the
> >valuable
> > > board real-estate. If anybody has come across any research that states
> > > otherwise in a peer-refereed publication I'd like to hear that.
> > >
> > > Regards
> > >
> > > Ihsan
> > >
> > >
> > > On 7/22/06, Giovanni Guasti <giovanni.guasti@xxxxxxxxxx> wrote:
> > > >
> > > > Kenny,
> > > > GND vias near the signal are not dedicated to return currents, but
they
> > > > are often used to optimize the impedance of the via.
> > > > As the via is a short transmission line, only the higher speed
signals
> > > > can benefit of the difference between an optimized via and a "usual"
> > > > via.
> > > >
> > > > You have to compare the higher frequency component of your signal,
its
> > > > wavelength and the via length. This will give you an idea of the
> > > > effective needing to optimize this short transmission line.
> > > >
> > > > Of course you could have a 133MHz signal with very sharp edges and
high
> > > > frequency components, even if it seems very unusual... In this case
it
> > > > would be wise to choose a slower transmitter!
> > > >
> > > > The rule is to understand if the via behaves like a transmission
line
> > > > for your signal or not, and in the first case to do the best to
reduce
> > > > impedance discontinuities.
> > > > Best regards,
> > > >         Giovanni
> > > >
> > > >
> > > > -----Original Message-----
> > > > From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> > > > On Behalf Of Lee Ritchey
> > > > Sent: 22 July 2006 18:36
> > > > To: Kenny Frohlich; si-list@xxxxxxxxxxxxx
> > > > Subject: [SI-LIST] Re: Current Return Vias
> > > >
> > > > Kenny,
> > > >
> > > > It is not true that you need a "return current" via next to each
layer
> > > > changing signal  via.  I continue to be amazed that engineers who
are
> > > > looked upon as SI experts say such things.
> > > >
> > > > Imagine you have a 4 layer PCB, such as the mother  board in a PC,
where
> > > > there are only two planes, one Vdd and one ground, where would such
vias
> > > > connect?  There have been billions of these made to date that work
just
> > > > fine and have very fast signals on them.  The return currents you
are
> > > > concerned about find their way from plane to plane through the
> > > > collection
> > > > of decoupling capacitors and interplane capacitance that you had to
> > > > engineer into the power delivery system in order to make it stable.
> > > > Focus
> > > > on this and the return currents take care of themselves.  EMI is
> > > > minimized
> > > > he same way..
> > > >
> > > >
> > > >
> > > >
> > > > > [Original Message]
> > > > > From: Kenny Frohlich <kenny_frohlich@xxxxxxxxx>
> > > > > To: <si-list@xxxxxxxxxxxxx>
> > > > > Date: 7/22/2006 6:45:56 AM
> > > > > Subject: [SI-LIST] Current Return Vias
> > > > >
> > > > > Dear Experts,
> > > > >   I understand that I need to provide ground vias next to via
> > > > explictly
> > > > for the purpose of letting return currents jump between layers.  I
know
> > > > it's a requirement for high speed signals, especially differrential
> > > > signals.  Is this also required for low speed single-ended signals
> > > > (133Mhz
> > > > or slower)? =20
> > > > >   If this is a requirement, what would be a good signal via to
ground
> > > > via
> > > > ratio? For example,  there are five signal vias within a 1 inch
area,
> > > > how
> > > > many ground vias do I need?
> > > > >   =20
> > > > >   Thank you
> > > > >   Kenny
> > > > >   =20
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