[SI-LIST] Re: Crosstalk - Impact on bus timing
- From: steve weir <weirsp@xxxxxxxxxx>
- To: ched_chang@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 25 Feb 2002 00:15:09 -0800
Chai,
The slide is correct.
To determine the impact, you need to know four things:
1) The crosstalk coefficient.
2) The rise/fall time of the signals.
3) The amplitude of the signals.
4) The voltage swing from high or low to the switching threshold
Find the aggressor slope from 2) and 3), and multiply by 1) to get the
delta slope. Add or subtract the delta slope to the victim nominal slope
to get the net rising / falling slope on the victim. Divide the voltage
swing 4) by the net slope to obtain the new switching delay. Subtract this
number from the value obtained with an unaffected trace to obtain the
timing shift.
There was also a paper delivered on this at DesignCon 2002, but I believe
you must pay for the proceedings to get it. The paper dealt with these
effects in chips and some software to estimate it. But, the physics apply
at the board level as well.
Regards,
Steve.
At 03:44 PM 2/25/2002 +0800, Ched-Chang Chai wrote:
>Hi All,
>I have some questions regarding the impact of crosstalk on bus timing.
>Referring to a presenataion slide, it states that crosstalk between adjacent
>bus bits affects edge speed, either make it slower or faster, depending on
>either EVEN (signal transitions at the adjacent traces are the same as the
>one at the victim trace) or ODD mode (signal transitions at the adjacent
>traces are opposite to the one at the victim trace) configuration is used.
>My questions are as below:
>(1) Given certain trace geometries and signal rise times, are there any
>equations which can be used to estimate this effect quantitatively?
>(2) Any good references on this subject?
>(3) I would appreciate if anyone could brief me the theory behind.
>Thank you very much in advance.
>--
>Regards,
>Chai
>
>
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