Dear All: Below is a discussion in the list before. I don't understand some of the ideas in it. Hope some experts can give me some explains. "Crosstalk in a bus isn't necessarily a bad thing. Large busses are limited by simultaneous switching delays (limited current in the chip supply inductors) into line impedances. Near-end crosstalk under SSO effectively raises the line impedance and reduces the SSO delay, compensating in part for the SSO and keeping timing more consistent." 1. What's simultaneous switching delays ? why Large busses are limited by simultaneous switching delays ? 2. Why near-end crosstalk under SSO effectively raises the line impedance? How raised line impedance reduces the SSO delay? Why raised line impedance can compensate in part for the SSO and keeping timing more consistent? 3. Under what situations, the crosstalk is useful? Thanks in advance. Your sincere help is highly appreciated. Zhenggang ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Zhenggang Cheng Ph.D Candidate Electrical and Computer Engineering Dept Duke University 130 Hudson Hall, POBox 90291 Durham, NC, 27708 919-660-5232(O) 919-218-5520(H) ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu