[SI-LIST] Re: Coupling THROUGH a plane?
- From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- To: "Boris Yost" <yost@xxxxxxxxxxxxxxxxxxx>
- Date: Fri, 07 Mar 2003 14:15:05 -0800
Boris,
Thanks for the update. Fantastic detective work!
best regards,
scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
Boris Yost wrote:
>Dear List:
>
> Q: When is unshielded twisted pair cable not shielded, not twisted, and
>not paired?!?
> A: When it is unshielded twisted pair RIBBON cable!!!
> The twisted part is twisted, but where you put the connectors has to be
>regularly and uniformly oriented and straight. Unless you are going real
>real far with the cable, the percentage of cable that is not twisted is
>probably 20%. That part couples like cheap ribbon cable.
> So my problem had nothing to do with "coupling THROUGH a plane". As a
>matter of fact, it had nothing really to do with the LVDS pair that had the
>bad symbol. A few clock earlier than my error, some noisy thing couples
>into the LVDS clock, probably an unlucky alignment of bits. It does a
>better job coupling into the complement line than the true line. The LVDS
>PLL gets nudged from where it should be and jitters. A few clocks later I
>get a bit error. The error happens to be in the "worst" pair of a basically
>good design. I fixed it by filtering the clock. I should go back and find
>the root cause of the noise and try to make it go somewhere else.
> The previously mentioned dip I believe is ground bounce and I'm still
>deciding whether it is bad enough that I must be rid of it.
>
>Boris
>
>----- Original Message -----
>From: "Boris Yost" <yost@xxxxxxxxxxxxxxxxxxx>
>To: <si-list@xxxxxxxxxxxxx>
>Sent: Friday, February 28, 2003 4:47 PM
>Subject: [SI-LIST] Coupling THROUGH a plane?
>
>
>
>
>>Dear List:
>>
>>I'm working on a persistent annoying bit error with LVDS. We had one
>>design that we made hundreds of and never had a problem. We copied the
>>
>>
>LVDS
>
>
>>receiver part (same parts and same layout) to a new design. Now I have a
>>bit error on both ordinary and torture test patterns that shows up on 10%
>>
>>
>of
>
>
>>boards. I have tracked it down to one particular symbol, and it turns out
>>that symbol has a dip of about 40% of signal swing in common mode voltage.
>>The eye diagram of the difference signal is wide open.
>>Now, while we copied exactly the LVDS, we didn't copy everything else.
>>Turns out, they put about 3 ordinary CMOS traces under the victim signal.
>>However, the victim and my supposed aggressors are separated by a solid
>>ground plane. (That is, it is as solid as anybody's ground plane ever
>>is--except for the via holes.) The LVDS traces are on the surface, and
>>
>>
>the
>
>
>>other traces are on layer 3 of a 6 layer board. The board that works
>>doesn't have traces there.
>>Should I be looking hard at this difference, or should I be looking at our
>>many other potential problems.
>>
>>Best regards,
>>Boris Yost
>>Mgr Electrical Engineering
>>Rainbow Displays
>>
>>
>>
>
>
>
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