[SI-LIST] Re: Copper Fill --- correction
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: scott@xxxxxxxxxxxxx
- Date: Thu, 13 Jun 2002 17:39:22 -0700
My equation below has an error.
The maximum via spacing should be:
2/(f * Vp)
This accounts for the half-wave resonance which occurs between vias.
regards,
Scott
Scott McMorrow wrote:
>Ray,
>
>When the separation of the copper fill from any signal is > 20 times the
>signal-to-plane spacing there is no effect on the signals. So, for 5 mil
>dielectric thickness, the fill area to signal trace clearance should be
>100 mils or greater. I would also suggest grounding each fill area at
>multiple points to eliminate possible EMI coupling problems.. At a
>minimum, use ground stitch vias at four corners to contain resonances of
>the fill area. For extremely high speed multi-gigahertz systems, the
>vias should be spaced a maximum distance apart of 1/(f * Vp) apart.
> Where f = the upper frequency of operation and Vp is the velocity of
>propagation of signals within the dielectric.
>
>For FR4 Vp is around 180ps/in. For 3.125 Gbps signallling the upper
>frequency you are concerned with is the 3rd harmonic of the switching
>frequency, 4.68 GHz. In this case, the maximum stitch via spacing would be
>1/(4.68e9 * 180e-12) = 1.18 inches.
>
>Best regards,
>
>Scott
>
>
>
>
--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
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