[SI-LIST] Re: Convergence problem after inserting detailed connectormodel
- From: Robert Haller <rhaller@xxxxxxxxxx>
- To: hassan@xxxxxxxx
- Date: Fri, 20 Feb 2004 08:45:11 -0500
Julia,
Hassan made some really good suggestions.
To solve "internal timestep too small", you need to be a detective.
Start with a ideal source on a single line of the connector model and
terminate all of the other leads.
Then add in pieces of your real circuit (that you have already verify
converges in an independent simulation) one piece at a time.
Check the results after each piece is added in and make sure they
correlate to expected results.
Larry Smith (I think?) made an excellent observation on the PDS thread.
You almost need to know the answer BEFORE you run the simulation and you
must make sure the simulation matches what you expect.
Simulate, Measure and Iterate works well with connectors too !
I will state the obvious, a bad model can create lots of problems, So
also provide feedback to your model provider (that you are having
convergence problems) and solicit their help..
regards,
Bob
--
Robert J. Haller (rhaller@xxxxxxxxxx)
Principal Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 15
Hassan O. Ali wrote:
> Julia,
>
> I've come across this problem so many times. I think it is caused by
> components in the connector model that have too small values. Small
> elements combined with big elements in the rest of your netlist result
> in an ill-conditioned matrix equation. An ill-conditioned matrix
> equation behaves differently with different solution methods. That
> explains why changing the solution method to Gear solves the problem
> sometimes.
>
> Here are a few things that I normally do when I face problems with
> connector models:
>
> 1. I make sure I terminate all un-used connector terminals with 50-ohm
> loads - on both sides (input and output)
> 2. I replace all insignificant resistor values (e.g. below 1e-4) with
> zero DC voltage sources
> 3. I connect 1G shunt loads to all the terminals
> 4. I add appropriate via parasitics (especially capacitance) to all the
> connector terminals
> 5. I run the simulation in stages and observe convergence issues:
> i) just the connector with ideal source and load on one pin
> ii) full netlist with no transmission lines between connector and
> the rest of the network (i.e. direct connection)
> ii) full netlist with lossless transmission lines (the T elements)
> between the connector and the rest of the network
> iii) full netlist with W-element transmission line models between
> the connector and the rest of the network
> 6. If only the connector model with ideal source and load runs, I
> generate a connector macro-model through frequency-domain S-parameters
> obtained using AC analysis.
>
> Hope that helps.
>
> Hassan.
>
>
> Nekrylova, Julia wrote:
>
>
>>Hello,
>>
>>
>>I've added a detailed connector model to my Hspice deck and started
>>getting
>>
>>"internal timestep too small" error messages. Before that the connector
>>was represented just by
>>
>>RLGC matrix model. Tried different fixes: reduced transition times, set
>>initial conditions,
>>
>>tried gear method, put shunt conductances and capacitances. Some times
>>in the past Accurate=1 and
>>
>>Converge=4 worked for me, but this time nothing seems to help.
>>
>>
>>
>>What else I could try? I am pretty sure there are lots of people on the
>>list who had similar problems
>>
>>with their spice decks after adding sophisticated interconnect models.
>>
>>What could be the most popular solution in this case besides talking to
>>the connector company application engineer?
>>
>>
>>
>>Thanks a lot,
>>
>>Julia
>>
>>
>>
>
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