[SI-LIST] Re: Controlling Plane-cap Anti-resonance
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Bradley Henson <Bradley_Henson-NR@xxxxxxxxxxxx>
- Date: Wed, 10 Sep 2008 10:20:53 -0700
Brad, please see discussion on Eric Bogatin's blog from 7/21/2008. For
a number of reasons it is becoming more and more important to manage the
transitions between the bypass network and packaged ICs, and the bypass
network / packaged ICs and the PCB plane cavities. The most common fix
for this is to select a capacitor or capacitors with mounted SRF in the
region of the parallel resonance to damp out the resonance. Just don't
overdo it. Getting just enough ESR is helpful here. The lower the
inductance of the compensating caps the better, another nice advantage
for X2Y parts. We've used them to compensate resonances up as high as
600MHz with excellent results.
Steve.
Bradley Henson wrote:
> Over the last year I've looked at a couple of designs with a similar
> problem. These are relatively small boards, less than 10 inches on a side.
> The power/ground pairs are considerably smaller, occupying maybe 3-4
> inches on a side. They can not use decoupling under the BGAs, so capacitor
> planes are used near the top layer just under the components to keep the
> loop inductance to the top-side decoupling minimized. Low inductance caps
> are used (e.g. IDCs) and the lowest possible inductance connections are
> used for the cap-to-plane. Super thin dielectrics are not used, but
> 2-3mils is typical for between the power/ground. Decoupling looked at both
> Deep-V and various multi-pole approaches using Target Impedance, popular
> in recent times. All of this corresponds to what I think is current good
> practice. If it matters, these are not particularly cost sensitive and
> typically have very little room (can't grow). Component technology
> includes contemporary FPGAs, SERDES, processors with DDR2 and so forth.
> The issue I've seen is that the higher values of plane capacitance
> resonate with the various inductances at a lower frequency than boards
> that don't use tailored cap-planes ( stripline or dual-offset power/ground
> plane configurations). The anti-resonant peak associated with the plane
> cap and the inductances peaks down near maybe 200MHz with a value high
> enough that it makes achieving a low target impedance much above 100MHz
> more than tough. I've looked at this in various tools including
> applications made expressly for decoupling, spreadsheets, SPICE and so
> forth. They all agree within reasonable limits that the peaks are there,
> and that it is not practical, at least in these cases, to throw enough
> high freq. caps at the peak to tame it.
>
> I have to think that others doing PDS analysis have run into this and I'm
> simply overlooking something? How can we decouple single-ended DDR2 I/O
> (example) signals with fundamental frequencies in the 200MHz - 300MHz
> ranges when the plane cap anti-resonant peak make the PDS impedance so
> tough to tame? What about core clocks running at several hundred MHz?
> Unfortunately, my analysis does not include on-package and on-die
> capacitance due to lack of vendor information. I think this may be
> significant. Your thoughts or experiences?
>
> Thanks
>
> Brad
>
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