[SI-LIST] Re: Conductor loss reduction at High Frequency
- From: steve weir <weirsi@xxxxxxxxxx>
- To: jeff.loyer@xxxxxxxxx
- Date: Thu, 30 Aug 2007 15:06:32 -0700
Jeff, fancy materials and processing as you note bring a whole slew of
engineering and economic challenges. The strong impetus is always going
to be to throw what just keeps getting cheaper at the problem: transistors.
Best Regards,
Steve.
Loyer, Jeff wrote:
> I'm afraid your question falls into an "under development..." bucket
> that I'm not able to say a whole lot about regarding specifics. From a
> high-level philosophical viewpoint, here's a thought or two...
>
> While we haven't had to worry about (or specify) loss (both conductor
> and dielectric), we don't have that luxury any longer. Loss plays a
> large role in the performance of today's busses. Usually loss is a bad
> thing, but it can help in some instances.
>
> We also don't have the luxury of throwing infinite amounts of money at
> the problem for low-profile conductors and low-loss dielectrics.
> Solutions must have comparable prices to past materials. This is very
> challenging.
>
> Even if we could spend lots of money for exotic materials (and I've had
> the luxury of doing that in a past job), those materials aren't
> risk-free either. They can have their own unique reliability issues,
> some of which may only surface under very high volume conditions.
> Moving away from tried-and-true is not to be taken lightly.
>
> Specifying loss is not a trivial endeavor either - do we differentiate
> between conductor and dielectric losses? At what frequency(ies)? How
> do we measure it in a HVM environment, so I get the same answer from
> suppliers throughout the globe? (CHEAPLY)
>
> How we specify control of loss on PCB's is an on-going topic which I
> think will take a lot of discussion/negotiation before all the details
> emerge.
>
> Disclaimer:
> The content of this message is my personal opinion only and although I
> am an employee of Intel, the statements I make here in no way represent
> Intel's position on the issue, nor am I authorized to speak on behalf of
> Intel on this matter.
>
> Jeff Loyer
>
> -----Original Message-----
> From: Aubrey_Sparkman@xxxxxxxx [mailto:Aubrey_Sparkman@xxxxxxxx]=20
> Sent: Thursday, August 30, 2007 9:35 AM
> To: Loyer, Jeff; si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Conductor loss reduction at High Frequency
>
> What I hear you saying is that, in addition to an impedance spec, we are
> going to have to add a Roughness (RMS) spec....
>
> Any proposals for initial ranges?
>
>
> Aubrey Sparkman=20
> Enterprise Engineering Signal Integrity Team
> Dell, Inc.=20
> Aubrey_Sparkman@xxxxxxxx=20
> (512) 723-3592
>
> "The ultimate measure of a man is not where he stands in moments of
> comfort and convenience, but where he stands at times of challenge and
> controversy." - Martin Luther King, Jr.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Loyer, Jeff
> Sent: Thursday, August 30, 2007 10:49 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Conductor loss reduction at High Frequency
>
> Oops - I meant to say "But not TOOOOOO rough".
>
> Jeff Loyer
>
> -----Original Message-----
> From: Loyer, Jeff=3D20
> Sent: Thursday, August 30, 2007 7:51 AM
> To: 'eric@xxxxxxxxxxxxxxx'
> Cc: si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Conductor loss reduction at High Frequency
>
> One of the ironic things about this is that for years we've been asking
> our board vendors to make the copper as rough as possible to maximize
> peel strength (and they've accommodated that). Now we need to tell them
> "But not TOOOOO smooth!".
>
> We need to strike a balance between smoothness for least loss, but rough
> enough to ensure adequate adhesion. And this will be different for
> inner vs. outer layers.
>
> Fab drawings are going to get even more convoluted in the near future...
>
> Jeff Loyer
>
>
> -----Original Message-----
> From: Eric Bogatin [mailto:eric@xxxxxxxxxxxxxxx]=3D20
> Sent: Wednesday, August 29, 2007 2:47 PM
> To: scott@xxxxxxxxxxxxx; Loyer, Jeff
> Cc: sridharam@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Conductor loss reduction at High Frequency
>
> I second Scott's important point. Above 1 GHz, skin depth is less than 2
> microns in copper. When the RMS surface roughness is larger than the
> skin depth, it affects conductor loss.=3D20
>
> Above 3 GHz, surface roughness can almost double conductor loss. In
> fact, the commonly used approximations for the impact from conductor
> loss, saturate at a factor of 2 increase to the resistance when the
> surface roughness is about 3 x skin depth.
>
> This means, even though your line width is 5 mils, it would have the
> conductor loss equivalent of a 2.5 mil wide line. The conductor loss can
> easily swamp the dissipation factor of even FR4, negating any benefit
> for low loss materials unless you are using very wide lines.
>
> If you want the biggest bang for the buck in evaluating conductors, try
> looking at surface treatments that allow smoother copper foils.
>
> --eric
>
> **************************************
> Dr. Eric Bogatin, President
> Bogatin Enterprises, LLC
> Setting the Standard for Signal Integrity Training
> 26235 w 110th terr
> Olathe, KS 66061
> v: 913-393-1305
> f: 913-393-0929
> c:913-424-4333
> e:eric@xxxxxxxxxxxxxxx
> www.BeTheSignal.com=3D20
> Fall 2007 Signal Integrity Training Institute EPSI, SIAA, BBDP Oct 8-12,
> 2007, San Jose, CA ****************************************=3D20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On
> Behalf Of Scott McMorrow
> Sent: Wednesday, August 29, 2007 4:11 PM
> To: jeff.loyer@xxxxxxxxx
> Cc: sridharam@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Conductor loss reduction at High Frequency
>
> Surface roughness is the largest contributor we've measured for=3D20
> conductor loss. There are certain low loss materials that are=3D20
> constructed with high tooth copper for maximum adhesion, which show=3D20
> enough loss to absolutely negate any benefit that the low loss (low
> tan=3D20
> delta) material would have had over materials with twice the
> dielectric=3D20 loss.
>
> Interesting stuff.
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> http://www.teraspeed.com
>
> TeraspeedR is the registered service mark of Teraspeed Consulting Group
> LLC
>
>
>
> Loyer, Jeff wrote:
>
>> My 2 cents available in the article below:
>>
>> http://pcdandm.com/cms/content/view/2572/95/
>>
>>
>> Jeff Loyer
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
>>
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>
>> On Behalf Of M Sridhar
>> Sent: Wednesday, August 29, 2007 5:08 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Conductor loss reduction at High Frequency
>>
>> Hi Members,
>>
>> What are the methods by which we can reduce the conductor losses at
>>
> high
>
>> frequency?(Loss due to skin effect, Dielectric losses etc.) Which is=20
>> the best conductor at higher frequency? in the range of 1-5
>>
> GHz
>
>> Thanks,
>> Sridhar
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--
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