[SI-LIST] Clock quality
- From: "Patel, Bhavesh" <BPatel@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 24 Aug 2001 16:55:35 -0700
Hi! I had a question regarding clocks being driven to two loads using one
o/p pin of the clock driver.
I have implemented this successfully in other designs where the clock driver
is driving two loads which are source terminated and the length of the
traces are almost equal to each other in order to account for the
reflections from the loads. The loads are the same i.e. the same type, mfgr
etc.
In this particular case, when I look at the clock at the i/p of the memory I
see the clcok sitting approximately 1V above ground. From, SI point view
this is not good because the i/p buffer of the load will see a signal that
is sitting above Vil.
I needed to know what could be causing this? I have temporarily used a pull
down at the receiver to bring the swing down to 0.5V and this way the
circuit works fine.
Any input appreciated.
Thanks
Bhavesh
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