[SI-LIST] Re: Clock jitter
- From: bbolton <bbolton@xxxxxx>
- To: k.kanakaraj@xxxxxxxxxxxxx, si-list <si-list@xxxxxxxxxxxxx>
- Date: Mon, 19 Sep 2005 20:16:02 -0400
Hi Kanak,
I would take a look at Tektronix JIT3 software package documentation. LeCroy
has some great jitter analysis tools.
Jitter is "ideally" a gaussian distribution an so it can be though of in
statistical terms. Jitter is the digital equivalent of analog phase noise.
Noise could have nearly any distribution, but you can make some statistical
shape assumptions and generalize it to some traceable metrics.
Jitter really is noise mixing onto the clock (or some other signal) from
various sources, such as power supply noise due to bypassing and semiconductor
circuit noise contributions.
Think of a gate such as a clock output buffer whose supply voltage rail is
being modulated with a noise function. The noise function on the rail will
map directly into the jitter (time variation) spectrum of the clock.
Different factors, such as decoupling quality and PCB-level noise issues are
directly related to jitter. How to get rid of the jitter is the main
question, and deciding on a consistant metric for jitter withing your group is
another decision that might save some sanity. Lead lengths of probes often
pick up noise which adds to apparent jitter, and what you percieve as the
jitter noise floor will be highly instrument and method related. You might
measure 500 ps of "jitter" when you are just measuring the noise floor of the
instrument in your lab. The real RMS (sigma) jitter with a better instrument
might be 50 ps or 2 ps.
Jitter analysis gets very interesting when you look at the jitter spectrum and
find out where your noise is coming from. Looking at the power spectral
density of the power supply rail with a spectrum analyzer can reveal noise
sources that couple into the jitter spectrum. So you could use a cheap
spectrum analyzer to get a hint about where your jitter is coming from, or you
could use some expensive analyzers and custom software packages to find the
same answer.
Good luck,
Bryce
Patents2Product, LLC
www.patents2products.com
>===== Original Message From k.kanakaraj@xxxxxxxxxxxxx =====
>-- Attached file included as plaintext by Ecartis --
>
>Hi All,
>
>Can anyone explain about clock jitter and the parameters associated with it?
>
>I find many parameters like
>1) Deterministic Jitter
>2) Random jitter
>3) RMS jitter
>4) Peak to peak jitter
>5) Accumulated jitter.
>6) Phase jitter
>
>or is there any literature available for the same?
>
>Thanks
>~Kanak
>
>
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