[SI-LIST] Re: Clock Jitter
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: "Pietz, Greg P" <greg.pietz@xxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 30 Jun 2009 18:03:20 +0100
hi
the manufacturers can increase the noises in at lest 2 ways:
1) some dielectric thicknesses in the stackup have been changed, signal
layers went further from the ground planes and closer to each other, so
increasing the crosstalk levels everywhere on your board. To avoid this,
specify exact materials and especially exact dielectric thicknesses in your
stackup, not just the layer-order and impedances. if you try it, the
manufacturers will aggressively try to convince you that its the worst thing
that you can do, and maybe that its over your knowledge (insult), and it
will be more expensive and you will get longer lead times. Even then you
should force the fixed stackup. Or at least before manufacture, the fab
should propose a stackup, (which should have exactly the same thicknesses),
and you have to authorise them to use that stackup. never let them to change
anything on your board just like that, even if they say its your interest
(becuase it is not).
check my appnote, chapter 3 (with internet explorer):
http://www.buenos.extra.hu/iromanyok/Accurate_Impedance_Control-2columns.pdf
2) if antipads become bigger, then at some dense via-arrays the ground plane
may be broken because of this, forcing the return currents away from their
natural paths, creating more reflections and crosstalk (into your clock from
other signals). you can maybe check the boards with x-ray, and compare.
regards,
Istvan Nagy,
Concurrent Technologies, Plc.
----- Original Message -----
From: "Pietz, Greg P" <greg.pietz@xxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, June 30, 2009 2:55 PM
Subject: [SI-LIST] Clock Jitter
> We have a board design using PCIe. The PCIe reference clock for each ASIC
> comes from a clock generator IC. On initial proto boards, build in the
> USA, the clock jitter was about 78ps or less on all boards tested. We
> then had boards built overseas and are seeing jitter of 90 to 100ps. This
> is greater then the spec allows and is causing problems with the link. I
> did a TDR of the clock traces and they are 100 ohms differential.
>
> For two of the board vendors I was able to make some changes to the design
> to get their jitter in spec. For the third vendor I have been unable to
> fix the jitter problem.
>
> The board stackup is the standard 6 layer design. The clocks all
> reference the ground plan.
> My question is what can a board vendor do to increase clock jitter.
>
> Thanks,
> Greg
>
>
>
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