[SI-LIST] Re: Clock Jitter
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Pietz, Greg P" <greg.pietz@xxxxxx>
- Date: Tue, 30 Jun 2009 07:13:43 -0700
Greg, how do you specify your board stack-up? Are you explicity or
generic? I think you want to understand the differences between the
boards which are likely to be dielectric thicknesses, and resin versus
glass content.
Things off hand that could bite you that have construction
dependencies: Excessive signal loss from long runs over crummy
dielectric, excessive even mode reflections, PDN impedance at the clock
driver, and cross talk from aggressor nets.
If you need this resolved right away, I recommend giving Al Neves a call
in our Portland office.
Good luck.
Steve
Pietz, Greg P wrote:
> We have a board design using PCIe. The PCIe reference clock for each ASIC
> comes from a clock generator IC. On initial proto boards, build in the USA,
> the clock jitter was about 78ps or less on all boards tested. We then had
> boards built overseas and are seeing jitter of 90 to 100ps. This is greater
> then the spec allows and is causing problems with the link. I did a TDR of
> the clock traces and they are 100 ohms differential.
>
> For two of the board vendors I was able to make some changes to the design to
> get their jitter in spec. For the third vendor I have been unable to fix the
> jitter problem.
>
> The board stackup is the standard 6 layer design. The clocks all reference
> the ground plan.
> My question is what can a board vendor do to increase clock jitter.
>
> Thanks,
> Greg
>
>
>
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