[SI-LIST] Re: Clock Jitter

  • From: "Michael Rose" <mrose@xxxxxxxxxxxx>
  • To: "Pietz, Greg P" <greg.pietz@xxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 30 Jun 2009 10:06:28 -0400

Greg,

Is the additional jitter DJ or RJ? If it's uncorrelated, you could look
at power noise. If it's DJ, you may want to look at the relative
magnitude of the impedance discontinuities (traces, vias, connectors).
Did you check trace coupons? Also, you might check if there is any
additional duty cycle distortion from the oscillator.

Good luck

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Pietz, Greg P
Sent: Tuesday, June 30, 2009 9:55 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Clock Jitter

We have a board design using PCIe.  The PCIe reference clock for each
ASIC comes from a clock generator IC.  On initial proto boards, build in
the USA, the clock jitter was about 78ps or less on all boards tested.
We then had boards built overseas and are seeing jitter of 90 to 100ps.
This is greater then the spec allows and is causing problems with the
link.  I did a TDR of the clock traces and they are 100 ohms
differential.

For two of the board vendors I was able to make some changes to the
design to get their jitter in spec.  For the third vendor I have been
unable to fix the jitter problem.

The board stackup is the standard 6 layer design.  The clocks all
reference the ground plan.
My question is what can a board vendor do to increase clock jitter.

Thanks,
Greg



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