[SI-LIST] Re: Clarification on Trace Routing over Plane Splits
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Dudi Tash <dudi@xxxxxxxxxxxxxxxxx>
- Date: Wed, 26 Mar 2014 15:39:43 -0400
But ... you might want to be sure that the signals avoid being routed over
unregulated power planes, if they exist in your design.
On Wed, Mar 26, 2014 at 3:34 PM, Dudi Tash <dudi@xxxxxxxxxxxxxxxxx> wrote:
> Hi Krunal,
> Based on some studies (both Simulations and Measurements), as long as
> you're under 2.5Gbps, passing over/under plane splits will have minor
> effect on your design.
>
> Best Regards,
> Dgtronix Ltd. I Founder & CEO I Dudi Tash
> eFax: +972-3-7256490 I Mobile: +972-54-6345629 I Office: +972-9-9660967
> www.dgtronix-tech.com
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> *This email contains confidential and proprietary information of Dgtronix
> Ltd.*
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> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Krunal Desai
> Sent: Wednesday, March 26, 2014 8:53 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Clarification on Trace Routing over Plane Splits
>
> Hi all -
>
> I have previously spent time in the high-speed realm, routing PCIe, SATA,
> HT, and many other high-speed digital signals where the thought of having
> them cross a reference plane split never even crossed my mind (i.e. never
> do it, and use stitching caps or vias if you absolutely must).
>
> I'm now working on some lower speed signals (the fastest is 10MHz with
> ~6ns rise time) but I have it firmly entrenched in my brain that I should
> still never cross plane splits. Unfortunately, I am very, very
> space-constrained in this application and due to its nature (power
> supply) I have split planes everywhere, leaving me a grand total of one
> layer available with an unbroken reference. I used that layer for all the
> 'fast' signals (SPI, clock).
>
> I have some essentially DC signals (Reset, power enables, things that get
> toggled once and then draw microamps of current) that I have triage'd to
> run over various plane splits. If I understand the teachings of Ritchie,
> Johnson, Archembault and others (hi guys!) the return path for these
> signals will follow the path of least resistance, not impedance, and
> leverage one of my large ground planes.
>
> So to sum: I am running DC/sub-Hz signals over plane splits, what can I
> expect from an EMI / noise perspective? I believe this is not ideal, but
> acceptable due to the very low frequency content of these signals, and the
> fact that return current will flow through my power planes, not immediately
> below the conductor.
>
> I have extensive decoupling capacitors present, and I plan on optimizing
> my PCB stackup to use thinner cores to improve high-frequency response of
> my power plane/GND plane pairs.
>
> Thanks,
> Krunal
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--
Scott McMorrow
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