[SI-LIST] Chip capacitance effect for SSN simulation - ANOTHER QUESTION FOR IBIS MODEL
- From: Cristian Gozzi <cristian.gozzi@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 21 Oct 2011 09:58:26 +0200
Hi folks
I'm sorry to bother you again on this topic
during some email exchange, I had some feedback regarding the non accuracy
of IBIS model to simulate SSN
I'm using Ansoft DesignerSI and I include IBIS model, then for each DDR I/O
I switch off the "ideal" power and I feed IBIS model with my PDN system
I got feedback that this is not accurate if IBIS model does not include I-T
table.
Looking at SI-LIST archive I found out an interesting paper from Sigrity,
attached for reference
So from my understanding it seems that voltage modulation of IBIS pwr pin is
possible due to pull-up / pull-down I-V curves
So if I have pwr noises on IBIS pwr pin I should also get modulated output
current and this effect output signal
Is my understanding correct?
If yes, which is now the lack of accuracy in IBIS model for simulating SSN?
as pointed out in this presentation, I got a confirmation about the missing
information of C_die parasitic effect
are there any other missing information compared to SPICE model?
Thanks in advance again for your support and feedback
Cheers
Cris
On 10/16/2011 2:25 AM, Cristian Gozzi wrote:
> > Hi SI members
> > I'm simulating DDR2 SSN for a Probe Card system
> >
> > for those that are not familiar with this application, Probe Card is an
> > hardware application to physical connect DIE pads/bumps at wafer level to
> > ATE system during Electric Wafer Sort
> > In my case Probe-Card is build by a vertical needles that touch DIE pads
> +
> > PCB
> >
> > During frequency domain analysis of my system, I got a strong PDN peak
> > impedance around 1GHz
> > This peak impedance was due to anti-resonance effect between PCB PDN
> system
> > and needle PWR parasitic effect
> >
> > so during time domain analysis I got a strong and unreasonable AC noises
> > also with only 2 switching DQ
> >
> > In my spice deck I only used IBIS model provided by silicon vendor and I
> > excluded RLC package effects, since my application is contacting directly
> > wafer.
> >
> > I think I should include chip power rail capacitance effect in order to
> > filter high freq noises.
> >
> > But my question is: which C and R value should I use?
> >
> > Is these value included in IBIS model?
> >
> > NOTE: consider that I had to reduce number of PWR needles used for HFSS
> > simulation, so I only selected those needles around my 8 DQ + 2 DQS
> >
> > So I think I should put a lower value of chip capacitance than total one
> >
> > Any comments from expert are more than welcome
> >
> > Thanks in advance
> >
> > Regards
> > Cris
> >
> >
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