[SI-LIST] Re: Capacitors arrays?worth it or not?
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Alan.Hiltonnickel@xxxxxxx" <Alan.Hiltonnickel@xxxxxxx>, JeanPierrePoulin@xxxxxxxxxxx
- Date: Tue, 23 May 2006 12:50:42 -0700
I agree that the spreadsheet method has same hazards. Namely failing to
show resonances between the plane capacitor and the parasitic inductance of
the discrete capacitors. It's good for a first order look at things. A
more precise method is to use a SPICE model. That will account for these
resonances, but it won't account plane resonances. The Ansoft and Sigrity
tools will. Perhaps there are other tools that will as well.
It is possible to achieve a reasonable impedance vs. frequency with about 5
values of capacitor and avoid any serious resonances. I've got many dozens
of measured results that show this. There is good correlation between
predicted and actual with the simulators named above and reasonable
correlation with the spreadsheet method.
> [Original Message]
> From: <Alan.Hiltonnickel@xxxxxxx>
> To: <JeanPierrePoulin@xxxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 5/23/2006 12:27:08 PM
> Subject: [SI-LIST] Re: Capacitors arrays?worth it or not?
>
> Hi Jean-Pierre,
> I've done spreadsheet analysis before, and it's a useful first
> approximation. The problem is that it is difficult to take resonances
> into account.
>
> I have not yet read Lee's book, and I'm not sure where he stands on
> capacitor selection technique (although I think it's safe to say he's in
> favor of it). There seem to be two schools of thought, both of which I
> have found useful. You can check the SI-List archives for more details.
> I'm sure I won't do justice to either method here.
>
> Under the "Big V" approach (championed most notably and ably by Steve
> Weir) you use the largest value capacitors you can find in any
> particular size and add them until you reach your target plane impedance
> over the frequencies of interest. Although I have used this
> successfully, you have to watch out for resonant peaks in the impedance
> profile caused by the inductance of a larger cap interacting with the
> capacitance of the next smaller cap.
>
> The distributed approach requires choosing multiple values in each size
> to create a flat (or nearly so) impedance profile. This approach was
> developed by Ray Anderson, Larry Smith, and Tanmoy Roy. The problem I
> find with this approach is that the end result can be an impractically
> large number of capacitors.
>
> Ultimately you need to simulate and measure. There are several good
> simulation tools available. Naming a few off my head, Cadence has a
> decent Power Integrity tool, as do SiSoft, Mentor, Ansoft and Sigrity
> (This is not a comprehensive list. Google: "Power Integrity"). For any
> of these tools to work well, you'll need good models. Once you've built
> the board, use a VNA to evaluate your power impedance. The results of
> that should inform your decisions on capacitor changes or design changes.
>
> I won't go into placement and connection methods here, I'm sure you're
> aware of how crucial it is to keep connection inductance from dominating
> capacitor package impedance. Steve's comments elsewhere in this thread
> have me wanting to revisit the array and X2Y caps to see if I'm missing
> something.
>
> Alan
>
> jeanpierrepoulin wrote On 05/21/06 10:05,:
>
> >Thanks Alan for the recommendations on a formal analysis...
> >
> >It did seem - given the sub 1ns rise time - that this was required
> >even if the two parts are right close to one another... so I've been
> >trying to improve on my previous approach (i.e. follow ref design
> >and 'sprinkle a few more caps just in case' methodology) to a more
> >scientific approach...
> >
> >Reading on the subject to improve the understanding and reach some
> >approximation to science, I have thus far adopted Lee Ritchey's
> >approach, added some theory from Dr. Howard Johnson and verified the
> >whole thing with an old Micron app note...
> >
> >However, the 'excel spreadsheet' that resulted is surely not optimal
> >and could induce us in some errors...
> >
> >Are there any tools / methodology you have seen in your travels that
> >can assist with capacitor selection for high-speed designs such as
> >ours?
> >
> >Many thanks!
> >
> > Jean-Pierre
> >
> >--- In si-list@xxxxxxxxxxxxxxx, Alan Hilton-Nickel
> ><Alan.Hiltonnickel@...> wrote:
> >
> >
> >>Jean-Pierre,
> >>
> >>You have some analysis to do, both electrical and mechanical.
> >>
> >>Keep in mind that as the form factor of the capacitor gets
> >>
> >>
> >smaller, the
> >
> >
> >>interconnect inductance becomes more dominant. This means that the
> >>lowest-inductance caps should generally be closest to the point of
> >>consumption (the chip). This often means underneath the chip. The
> >>
> >>
> >arrays
> >
> >
> >>and the odd form-factor caps may simply not be placeable without
> >>eliminating power or ground vias, which at some point defeats the
> >>purpose of using low-inductance caps since it increases the
> >>
> >>
> >inductance
> >
> >
> >>of the power-plane connection.
> >>
> >>I've often seen the arrays and X2Y/LICCs used most effectively on
> >>
> >>
> >the
> >
> >
> >>package, not the board. The higher cost of the parts is a key
> >>
> >>
> >factor as
> >
> >
> >>well.
> >>
> >>Good luck with this.
> >>
> >>Alan
> >>
> >>
> >
> >
> >
> >
> >
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> >
>
> --
> Alan Hilton-Nickel
> Signal Integrity Engineer
> Sun Microsystems Inc.
> Netra Systems and Networking
> Newark, CA
>
>
>
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