[SI-LIST] Re: Capacitors and Anti-resonance
- From: Istvan Novak - Board Design Technology <inovak@xxxxxxxxxxxxxxxxxxx>
- To: Daniel.Paradis@xxxxxxxxxx
- Date: Tue, 29 Jul 2003 10:33:25 -0400 (EDT)
Daniel,
If you are worried about capacitor-capacitor antiresonance, it usually occurs
at
low enough frequencies that physical separation on the board can be neglected.
You can try 'what-if' scenarios with the assumed capacitors using either SPICE
or spreadsheets that plot the cumulative impedance of multiple capacitors.
Regards,
Istvan Novak
SUN Microsystems
Delivered-To: si-list@xxxxxxxxxxxxx
From: "Paradis, Daniel" <Daniel.Paradis@xxxxxxxxxx>
To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Capacitors and Anti-resonance
Date: Tue, 29 Jul 2003 09:57:46 -0400
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I started to use only 0.1uF decoupling caps on our latest designs.
This is to avoid the anti-resonance effect that occurs when using 2
different caps near each other.
The rule of thumb is to use the largest cap available for the package.
So far I got good results, but I was wondering....
Is-there a simple way to determine the distance between 2 different
decoupling caps beyond which there is no anti-resonance effect?
In other words..
Say that I stick to this general rule of using only one cap.
It seems to me that there could be exceptions to that rule.
In the case of a high speed clock buffer for instance;
I could need 0.0047uF instead of 0.1uF
If this clock buffer is located far from other parts of the design.
Can I avoid anti-resonance?
Daniel Paradis
Staff Electrical Engineer
Digital Subscriber Networks
Scientific-Atlanta, Inc.
5030 Sugarloaf Parkway, ATL 1.3468
Lawrenceville, GA 30042
Tel: (770) 236-7896
Fax: (770) 236-2449
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Istvan Novak Sun Microsystems, Inc.
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