Hi All, For a low-cost implementation we are looking to drive SSTL_18 receivers on our chip with standard 1.8V single -ended logic for a 100Mhz clock. I have usually used LVPECL for this type of application. I checked it should be OK to drive 1.8V levels to the SSTL_18 inputs. The remaining question is about the speed / drive performance of the standard logic. Can I use ALVC244 / 245 type of buffers? They have ~ 6mA symmetric current drive. They dont spec any fMAX or Max data rate info. There is such info on some TI devices (SN74AVC8T245, >170Mbps @ 1.8V operation) but they spec a load of 15pF+ 2K. The ALVC buffer specs its load at 30pF+500 ohms. So would they be comparable. I have downloaded some IBIS models of the buffers but I dont have easy access to any simulation tool. Has anybody done this or anything similar. Thanks for any help, Jai Warrier __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu