[SI-LIST] Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic

  • From: Jai Shanker <jswarrier@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 21 Feb 2006 23:38:11 -0800 (PST)

Hi All,

For a low-cost implementation we are looking to drive
SSTL_18 receivers on our chip with standard 1.8V
single -ended logic for a 100Mhz clock. 

I have usually used LVPECL for this type of
application. 

I checked it should be OK to drive 1.8V levels to the
SSTL_18 inputs. The remaining question is about the
speed / drive performance of the standard logic.

Can I use ALVC244 / 245 type of buffers? They have ~
6mA symmetric current drive.

They dont spec any fMAX or Max data rate info. There
is such info on some TI devices (SN74AVC8T245,
>170Mbps @ 1.8V operation) but they spec a load of
15pF+ 2K. The ALVC buffer specs its load at 30pF+500
ohms. So would they be comparable.

I have downloaded some IBIS models of the buffers but
I dont have easy access to any simulation tool.

Has anybody done this or anything similar.

Thanks for any help,
Jai Warrier

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