[SI-LIST] Re: Can SSN be restrained by board decaps?
- From: Neo <neoflash2008@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx, xuzhengrong <Zhengrong.Xu@xxxxxxxxxx>
- Date: Mon, 22 Dec 2008 18:29:50 -0800 (PST)
Zhengrong:
I think a few conditions for your simulation might worth being re-evaluated.
1. L-pkg might be near 10nH for long bonding wire. However, the whole chip
will have more than 1-pair of power/gnd pin pairs, so the effective inductance
should be much lower.
2. Cdie is difficult to estimate since there are also a large amount of
device parastic loading.
Furthermore, there is a "difficult to model" damping resistor in parallel
with Cdie and Lpkg. This damping resistor comes from on-die circuits consume
power. The oscilation between Lpkg and Cdie should be well damped in normal
conditions.
Regards,
Neo
--- On Wed, 5/7/08, xuzhengrong <Zhengrong.Xu@xxxxxxxxxx> wrote:
From: xuzhengrong <Zhengrong.Xu@xxxxxxxxxx>
Subject: [SI-LIST] Can SSN be restrained by board decaps?
To: si-list@xxxxxxxxxxxxx
Cc: yang@xxxxxxxxxx
Date: Wednesday, May 7, 2008, 4:19 AM
Hi all,
In a test, I find there are large ringings on some DDR control signals
occasionally.
According to the timing diagram, I suspect SSN leads to the large ringing.
And the spice simulation result which I imitate SSN mechanism looks like the
test waveforms.
I think there is a resonance generated by C_die and package parasitics
(L_pkg dominantly).
I derive the resonance frequency from the ringing period and add several
corresponding decaps near the chip for improving the PDN.
It seems these decaps hardly have effect on SSN.
Since the L_pkg is usually about 10nH if the package is bad designed, it
almost separate the effect of PDN on die side from board decaps on mega Hz,
can the resonance be improved by board caps?
Appreciate any idea that those have experience on SSN and PDN co-design
could share.
Best Regards,
Zhengrong
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