[SI-LIST] Re: Cable grounding scheme

  • From: chen_jinhua@xxxxxxx
  • To: <Chris.Cheng@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 16 Aug 2006 09:10:12 -0400

Chris, That is exactly the problem I am facing. One design has to work
for GigE, iSCSI, FC, copper and optical etc. I am trying to understand
the reasons behind the different specs such as GigE and FC. In my
opinion, if the solusion is better in GigE, it also should be better in
FC. Physics is physics. It is not going to change per spec. If it is
copper cable, how to design and match the cable chassis/logic grounds to
connector chassis/logic grounds is also critical.

Ishan, if we use many vias to stitch the chassis ground to logic ground,
why should we separate them? If use capacitors to stitch them together,
it makes more sense. But as you mentioned, capacitor has its frequency
limitations. Does it work at high frequencies (> GHz)?

Thanks!

Jinhua

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Chris Cheng
Sent: Wednesday, August 16, 2006 2:06 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Cable grounding scheme

We can argue about tying chassis to logic ground here or there till
everyone faces turn blue but specs like Ethernet calls out specifically
for isolated chassis from logic ground on RJ45. FC-PI CHANGES from DC
short between logic and chassis (in optical modules) to complete
isolation (in quad lane connector). So how do you dictate a system that
support iSCSI and FCAL at the same time ?
To make things more fun, what are you going to do with peripherals like
disk drives and cdrom ? Have you ohm out your disk drive chassis and
your disk cable ground lately ? Do you even see them being consistent
between different vendors ?


-----Original Message-----=20
From: si-list-bounce@xxxxxxxxxxxxx=20
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of chen_jinhua@xxxxxxx=20
Sent: Tuesday, August 15, 2006 9:13 AM=20
To: erdinih@xxxxxxxxx; xileil@xxxxxxxxxxx=20
Cc: si-list@xxxxxxxxxxxxx=20
Subject: [SI-LIST] Re: Cable grounding scheme=20


Ihsan=20
 =20
If I understand your email correctly, you still use separate chassis and

logic grounds. But you use many many stitching points to connect them=20
together. If you consider the high speed cable application. It will=20
impact SI. If the cable does not have separate logic and chassis=20
grounds. Cable reference is chassis ground when it connects to the board

connector. From connector to semiconductor chips, there will be a=20
reference interruption because chip references to logic ground. Depends=20
on how bad of the reference interruption, the SI impacts will vary. If=20
the signal-point connection is used, I would guess the SI impact is=20
huge.=20
 =20
This brings an old question: single-point connection vs. many many=20
points of connections, which one we prefer for high speed SI and EMI? Or

it depends ...=20
 =20
Thanks!=20
 =20
Jinhua=20
________________________________=20

From: Ihsan Erdin [mailto:erdinih@xxxxxxxxx]=20
Sent: Tuesday, August 15, 2006 9:40 AM=20
To: Xilei Liu=20
Cc: chen, jinhua; si-list@xxxxxxxxxxxxx=20
Subject: Re: [SI-LIST] Re: Cable grounding scheme=20


Celine,=20
 =20
First of all, I want to express my apologies to Jinhua for -kind of-=20
hijacking his topic for a potentially flaring issue.=20
I think this issue goes as far back as the debate over single-point=20
vs.multi-point connection between chassis and digital grounds. As such,=20
it is more of an conducted/radiated emission problem than SI. The=20
dilemma is while single-point connection could be justified by the fact=20
that it avoids very low frequency common mode (noise) currents from=20
creeping into the power line, in order to cut down on the radiated=20
emissions at high frequencies, multi-point connection is strictly=20
required between the two reference systems. In his "EMC and printed=20
Circuit board design theory and layout made simple" book, for example,=20
M. Montrose suggests stitching the two reference systems at a distance=20
of lambda/20, with lambda being the wavelength of the highest frequency=20
component of the spectrum of the system. The book was published in 1999.

With today's multi-gigahertz systems, it's impossible to achieve such a=20
design goal and it's an overkill at any rate. But the necessity of=20
multi-point connection is not a debate any more. Some designers try to=20
find a mid-way by connecting the reference systems with high frequency=20
caps but the boards are already overly-populated by the same type of=20
caps used for decoupling and there's the issue of parasitic inductances=20
that defeat the purpose. Today, the commonplace approach, at least in=20
the designs that I observe, is to suppress the low frequency CM currents

with power line filters and directly connect the chassis and digital=20
grounds at practically as many points as possible against radiated=20
emissions. =20
If you want to see some numbers and charts to support these ideas, in=20
"EMI and Troubleshooting Techniques" book, M. Mardiguian gives a very=20
good example that compares the two grounding strategies.=20
 =20
Regards,=20
 =20
Ihsan =20


On 8/15/06, Xilei Liu <xileil@xxxxxxxxxxx> wrote:=20

        Hey, Ihsan,=20
       =20
        I've ever seen notes that published in the past in 2002, saying=20
that"we=20
        learned from NRAO engineers that it is both feasible and=20
advisable to=20
        physically separate digital circuits from analog systems, and to

interpose a=20
        minimum of two levels of Faraday shielding acting in series."=20
From my point=20
        of view, it should be easier to employ different EMI solutions=20
for power=20
        line and signal line separately when the digital/analog grounds=20
are=20
        separated and connected somehow at a single-point. What will be=20
the problems=20
        in terms of SI? Welcome your 'fight back' so that I can learn=20
more ;)=20
       =20
        Regards,=20
        Celine=20
       =20
       =20
        >From: "Ihsan Erdin" <erdinih@xxxxxxxxx>=20
        >Reply-To: erdinih@xxxxxxxxx=20
        >To: chen_jinhua@xxxxxxx=20
        >CC: si-list@xxxxxxxxxxxxx=20
        >Subject: [SI-LIST] Re: Cable grounding scheme=20
        >Date: Tue, 15 Aug 2006 06:29:32 -0400=20
        >=20
        >This question makes me wonder if there're any designers left=20
who still=20
        >separate logic ground from the chassis ground in high-speed=20
digital circuit=20
        >design -and on what basis? I thought this whole issue of=20
chassis vs. logic=20
        >ground was something of the past.=20
        >Regards,=20
        >=20
        >Ihsan=20
        >=20
        >On 8/14/06, chen_jinhua@xxxxxxx <chen_jinhua@xxxxxxx > wrote:=20
        > >=20
        > > Hi,=20
        > >=20
        > > I have a few general questions about the high speed cable=20
grounding=20
        > > scheme. It could impact both SI and EMI. I would like to=20
have your=20
        > > inputs about this issue.=20
        > >=20
        > > Scheme 1: cable does not separate logic ground and chassis=20
ground. But=20
        > > when it connects the system/boards, the system/boards have=20
separate=20
        > > logic ground and chassis ground. How do you separate/connect

the logic=20
        > > ground to chassis ground in boards? What is the pros and=20
cons for SI=20
        > > and/or EMI?=3D20=20
        > >=20
        > > Scheme 2: Cable keeps separate logic ground and chassis=20
ground.=20
        > > System/boards also keep the separate logic and chassis=20
ground. Cable=20
        > > logic ground and board logic ground connects, and chassis=20
connects the=20
        > > chassis ground. How do you separate/connect the logic ground

to chassis=20
        > > ground in boards? What is the pros and cons for SI and/or=20
EMI?=20
        > >=20
        > > Do you prefer scheme 1 or scheme 2? What is the pros and=20
cons of scheme=20
        > > 1 vs. scheme 2 for SI and/or EMI? Does SI and EMI have=20
conflict=20
        > > requirements?=20
        > >=20
        > > Thanks!=20
        > >=20
        > > Jinhua Chen=20
        > > SI of Hardware Engineering=20
        > > EMC Corp.=20
        > >=20
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