[SI-LIST] Re: CPW designs
- From: Jim Nadolny <jim.nadolny@xxxxxxxxxx>
- To: "shlepnev@xxxxxxxxxxxxx" <shlepnev@xxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 16 Feb 2012 18:47:29 +0000
Excellent -
Thanks as always Yuriy
jn
-----Original Message-----
From: Yuriy Shlepnev [mailto:shlepnev@xxxxxxxxxxxxx]
Sent: Wednesday, February 15, 2012 6:20 PM
To: Jim Nadolny; si-list@xxxxxxxxxxxxx
Cc: Justin Fleace
Subject: RE: [SI-LIST] CPW designs
Jim,
Line configuration you intend to use is called conductor-backed CPW. There are
a lot of parameters to consider designing CB-CPW for high-speed applications.
Comparing to simple micro-strip configurations, it has some advantages (lower
dispersion, no transitions through,...) and disadvantages (mode conversion,
possible higher losses, ...) [1]-[3]. In general, it is much easier to make it
worse than microstrip.
For instance, to suppress possible common mode in CB-CPW configuration [4], you
have to put sufficient number of stitching vias connecting two coplanar
reference conductors with the common reference conductor below [1]. Distance
between vias along the wave propagation direction and in the cross-section
should be close to a quarter of wavelength at the highest frequency of
interest. That is about 70-80 mil for 20 GHz frequency range and 35-40 mil for
40 GHz. The mode conversion in CPW takes place at the discontinuities.
Electromagnetic analysis of CPW as quasi-periodic structure and CPW
discontinuities may be a good idea.
References:
1) W.R. Deal, Coplanar waveguide basics for MMIC and PCB design, Microwave
Magazine, v. 9, No4, 2008, p. 120-133.
2) R. W. Jackson, "Coplanar waveguide vs. microstrip for millimeter wave
integrated circuits," IEEE MTT-S, pp. 699-702, June 1986.
3) G. Gronau, A. Felder, Coplanar-waveguide test fixture for characterization
of high-speed digital circuits up to 40 Gbit/s, Electronics Letters, v. 29, No
22, 1993 , p. 1939 - 1941.
4) R. W. Jackson, Mode conversion at discontinuities in conductor-backed
coplanar wavguide, IEEE Trans. On MTT, 1989, v 37, No 10, 1582-1589.
Best regards,
Yuriy
Yuriy Shlepnev, Ph.D.
President, Simberian Inc.
3030 S Torrey Pines Dr. Las Vegas, NV 89146, USA Office +1-702-876-2882 Cell
+1-206-409-2368
Skype: shlepnev
www.simberian.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Jim Nadolny
Sent: Wednesday, February 15, 2012 6:35 AM
To: si-list@xxxxxxxxxxxxx
Cc: Justin Fleace
Subject: [SI-LIST] CPW designs
Greetings -
Need some PCB fab practices guidance...
I'm looking at designing a co-planer waveguide on a 4 layer, lower cost
FR-406 substrate. THE CPW structure is on layer 1, layer 2 is a ground plane
but it is "far" away, the fields are coupled to the co-planer ground, not
really through the substrate to the layer 2 ground.
Anyway - my PCB vendor tells me that the best dimension control is to use
1/2 ounce copper and no plating on the layer 1 traces. I'm cool with that, but
we are wondering if the lack of plating on layer 1 leads to long term
reliability problems. The bare copper will have solder mask over it, but it
seems like you would have corrosion, whiskers, dendrites or something bad.
Any thoughts on bare copper on layer 1? How about thoughts on CPW structures
for high speed digital apps?
Jim Nadolny
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