[SI-LIST] Re: CPW designs
- From: Jim Nadolny <jim.nadolny@xxxxxxxxxx>
- To: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 15 Feb 2012 15:33:01 +0000
Thanks Gert, that helps
Correct on the additional step...the vias are plated but the other areas of the
PCB are covered. This was the vendors recommendation.
-----Original Message-----
From: Havermann, Gert [mailto:Gert.Havermann@xxxxxxxxxxx]
Sent: Wednesday, February 15, 2012 10:14 AM
To: Jim Nadolny; si-list@xxxxxxxxxxxxx
Cc: Justin Fleace
Subject: AW: CPW designs
Hi Jim,
I'm a bit confused.
Usually if traces are covered with solder mask, they don't get any surface
finish (ENIG, OSP or whatsoever). Only the open areas get a surface finish as
it is produced after the soldermask, and the solder resist takes care about
corrosion in the other areas.
Whisker is only an issue for Tin finish, especially when it is applied to
mechanical stress (compliant pin, etc.).
It is true, that the best impedance control on layer 1 is when you don't use
any plating, but as soon as you place any vias in your design, there is a
copper plating process that will work against your tolerancing. There are
techniques to cover areas of your PCB while thru plating, but that's an
additional step and thus doesn't fit into "standard" production lines. Anyhow,
Maybe that's what he meant.
Surface finish like ENIG or OSP will just add few micro meters to your trace
and GND path and doesn't really affect the impedance in any significant way
(not even for CPW).
I never used CPW in digital designs due to the amount of real estate needed.
Tight etching tolerances are another reason not to go this path, but that's
just my two cent .
BR
Gert
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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Jim Nadolny
Gesendet: Mittwoch, 15. Februar 2012 15:35
An: si-list@xxxxxxxxxxxxx
Cc: Justin Fleace
Betreff: [SI-LIST] CPW designs
Greetings -
Need some PCB fab practices guidance...
I'm looking at designing a co-planer waveguide on a 4 layer, lower cost FR-406
substrate. THE CPW structure is on layer 1, layer 2 is a ground plane but it
is "far" away, the fields are coupled to the co-planer ground, not really
through the substrate to the layer 2 ground.
Anyway - my PCB vendor tells me that the best dimension control is to use 1/2
ounce copper and no plating on the layer 1 traces. I'm cool with that, but we
are wondering if the lack of plating on layer 1 leads to long term reliability
problems. The bare copper will have solder mask over it, but it seems like you
would have corrosion, whiskers, dendrites or something bad.
Any thoughts on bare copper on layer 1? How about thoughts on CPW structures
for high speed digital apps?
Jim Nadolny
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