[SI-LIST] CAF issue or not?

  • From: "Filion, Marc-Andre" <marc-andre.filion@xxxxxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 15 Dec 2011 14:25:07 -0500

Hi,
I'm looking for a document that could give me practical detail about CAF for 
low voltage signaling (<24V). The paper that I've read so far are focuses on 
high voltage. How can we avoid that CAF affect serdes signal (like 1 GbE or 
SATA)?

PCB fab recommend 19.5 mil separation minimum between drill hole wall. 

 

My guess is that CAF will not affect the signal before any part on the PCB will 
reach MTBF. 

 

What's your opinion on this?

 

Best regards,

 

 

Marc-André Filion | Hardware designer | Kontron Canada | T 450 437 5682 x2243 | 
E marc-andre.filion@xxxxxxxxxxxxxx <mailto:marc-andre.filion@xxxxxxxxxxxxxx>  

Kontron Canada Inc
4555 Rue Ambroise-Lafortune
Boisbriand (Québec) J7H 0A4

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