[SI-LIST] Re: Bypass Capacitance?
- From: "Traa, Boris" <boris.traa@xxxxxxxxxxx>
- To: "ebj@xxxxxxxxxxxxxxxx" <ebj@xxxxxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 12 Mar 2012 10:40:34 +0000
Dear All,
If the decoupling has to be efficient for low and high frequencies you can put
a small ceramic capacitor in parallel with an Elcap in such a way that the ESR
is appropriated to suppress resonance between ESL and ceramic capacitance.
In case of on chip decoupling you have to be careful with external decoupling.
Below the resonance frequency the RF current is bypassed by the external
decoupling capacitor instead off and as such EMI will increase.
Kind regards
Boris Traa
System design engineer EMC
It's the currents that make circuits work or fail.
Philips Innovation Services/EMC center
Room 2.020
High Tech Campus 26
5656AE Eindhoven, The Netherlands
Tel: ++ 31 40 27 43766
Fax: ++ 31 40 27 42224
E-mail: boris.traa@xxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Elya B. Joffe
Sent: Monday 12 March 2012 11:16 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Bypass Capacitance?
Dear all,
From what I recall from Howard Johnson's teachings (which I find much rational
in), I recall the following:
* Once you have chosen a size (and technology) of a capacitor
(primarily ceramic) take the largest capacitive value you have in
that package. You have already paid your dues in terms of ESL
(inductance).
* There is no benefit in paralleling various values of ceramics (e.g.,
1nF, 10nF, 100nF), as a corollary of the previous bullet. If you
use, for instance. 0402 package X7R capacitors, then in the higher
frequencies, their inductance is equal almost (based on package) so
you achieve very little improvement at the higher frequencies, at
most you achieve the ESLs in parallel; in the lower frequencies,
where capacitance dominates, what is the benefit in
1nF||10nF||100nF? After all, that is almost 100nF? I prefer to
parallel equal values (maximum per package).
* If you parallel caps with different ESLs (say 1nF @ 0402, 10nF @
0603 and 100nF @ 0805 - not that there is a reason for those sizes
in those values...), you WILL encounter parallel resonances between
ESLs of the larger caps and the capacitance of the smaller caps...
Regretfully (?!?) ceramic caps have very little ESR, so you may
experience a relatively high-Q parallel resonance... The fact that
this might happen in the vicinity of the switching device, where a
very broadband spectrum of delta-I/SSN exists, might even worsen the
outcome of this mechanism... Normally, the PDN will include bulk
caps at the input to the board, and those should address the lower
frequencies, so I see no reason to address the lower frequencies at
the vicinity of the switching devices. However, containment of high
frequency noise near the switching device is definitely beneficial...
* Regretfully, today there is a trend of using large (up to 22uF)
ceramic caps instead of tantalum, for "bulk capacitance. These add
"double trouble". Because of their large value their package is very
large, this their ESL is relatively HUGE... On the other hand, being
ceramic results in a very low ESR, so resonances are not suppressed
very well. I have actually seen cases where designers have added
small resistance in series with the large ceramic caps (emulating
the "natural" ESR of the tantalum caps...).
Just a few comments which I hope you may find useful.
Cheers,
Elya B. Joffe
On 3/11/2012 4:45 AM, Rick Collins wrote:
> First, let me say that I am no expert in power distribution system
> (PDS) design. I took a class with Lee Ritchey a few years back and
> tried to absorb everything he taught in that class, which PDS was a
> small part of. There were several points he made which stuck with me.
> We'll see how well I remember...
> 1) To be effective, the impedance of the PDS has to be adequately low
> across the frequency spectrum. Using a single value or type of
> capacitance won't give you that in most situations because capacitors
> are capacitive below their resonance and the impedance rises.
> Capacitors are inductive above their frequency of resonance and the
> impedance also rises. Larger values of electrolytic or tantalum
> capacitors are used to get low impedance at lower frequencies.
> Ceramic caps provide low impedance at higher frequencies. Using power
> planes to form capacitors provides low impedance across a range of
> very high frequencies that discrete capacitors can't provide.
>
> 2) Discrete capacitors have effective series resistance (ESR), even
> ceramics, which will mitigate the anti-resonance peak in impedance
> created when more than one value/type of capacitor is used. If
> multiple values of ceramic capacitors are used (more than two) the
> peaks are typically well mitigated. The power planes also have some
> effect in this but I seem to recall it was rather complicated with
> lots of ripple at very high frequencies (> 1 GHz), possibly having to
> do with reflections at the edges of the board, standing waves perhaps?
> What I took away from this was to use 1, 10 and 100 nF ceramic caps in
> addition to the power planes and you should be good. You don't need
> TONS of each part. Lee showed us how to calculate the requirement,
> but it was based on knowledge of the current spikes of your chips. If
> you don't know that there is no way to actually know what your PDS
> requirements are. I've never seen this data on any of the chips I
> use...
>
> 3) When good power planes are used, discrete capacitors do not need to
> be extremely close to the chip they are decoupling. In essence the
> distance to the cap creates a "delay" in action while the E field
> propagates to the cap and back to the chip. The capacitance of the
> power plane provides adequate decoupling during this delay time.
> Think of the power plane as a very low impedance transmission line.
> Lee actually constructed a test board and measured the results as the
> decoupling cap was placed up to more than an inch away from the chip
> (maybe as much as three inches?). The difference in voltage variation
> at the chip was small.
>
> I hate to be spouting all this off because I have not had a lot of
> opportunity to verify it. I may have learned some of it wrong. But I
> am sure it will get a good vetting here and I'll find out if I did
> learn any of it wrong.
>
> BTW, in case you haven't figured it out, I highly recommend Lee's
> class at speedingedge.com
>
> Rick
>
>
> At 04:34 AM 3/11/2012, Aaditya Kandibanda wrote:
>> Hello Rick, thank you very much, I am somewhat confused about the
>> ground plane and power plane capacitance which is formed because of
>> stack up, what is its importance?
>>
>> On Sat, Mar 10, 2012 at 11:22 PM, Rick Collins
>> <<mailto:gnuarm.2006@xxxxxxxxx>gnuarm.2006@xxxxxxxxx> wrote:
>> I don't think it can hurt the devices you are trying to supply power
>> to, but some voltage regulators can be sensitive to low effective
>> series resistance (ESR) capacitors, like ceramic caps. If you
>> provide too many of the low ESR caps the total capacitance can
>> destabilize the regulator to the point of oscillations. If this is a
>> problem, they should tell you the upper limit of capacitance to use.
>> Rick
>> At 03:53 AM 3/11/2012, Aaditya Kandibanda wrote:
>>> Hello Everyone,
>>> I have a doubt on bypass capacitors, will there be any specific
>>> limit to the capacitance I can use for bypassing? what if my bypass
>>> capacitance is very large value? will it be okay?
>>>
>>> Thank you in advance,
>>> Aaditya
>>>
>>>
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