[SI-LIST] Re: Building a PBRS generator?

  • From: Hal Murray <hmurray@xxxxxxxxxxxxxxx>
  • To: steven@xxxxxxxxxxxxxxxxxxxx
  • Date: Mon, 15 Mar 2004 20:18:27 -0800

There is a good writeup of LFSR type random number generators in Horowitz and 
Hill: Art of Electronics.   Xilinx has a good app note with a big table of 
polynomials that don't need many XOR gates.  (aka few 1s in the generating 
polynomial)

Basically, an N bit LFSR will generate all patterns of N bits except for the 
all 0s case.  So with that circuit, you will get 23 1s in a row, 22 0s in a 
row...  They are a great tool for testing serial links.

Use a bigger polynomial if you want longer runs of 1s or 0s.  Use a smaller 
polynomial if you clock recovery can't take long runs of 0s.


> We'd like to build as fast a circuit as we can using readily available
> parts, such as the ON Semi MC100EL31, which will run up to 2.8 GHz.

How fast do you expect it to run?

The 2.8 GHz for the EL31 is a "typical" number,  think "marketing" rather 
than designing real circuits.

Let's use worst case numbers at 25C.  Clock-to-out is 590 ps.  Setup is 150 
ps.  So if you put a bunch of them in a chain, that's a max frequency of 1.35 
GHz.  That's before you add the XOR gate or any delays for wiring.  It also 
assumes no clock skew.

Prop time on the 100EL07 XOR gate is 260 ps.  That slows things down to an 
even GHz.  (It's worth checking my arithmetic and my copying numbers from the 
data sheets.)

I'm ignoring the mux.  You don't need it if all you want to do is go fast and 
find problems.  It might be handy if you want to reproduce a problem, but if 
you are going fast the pattern will repeat soon enough.  (2^23 => 2^3*2^20 => 
8*million.  If you are running at 1 GHz it will repeat 1000/8 times per 
second.)


If I wanted to build something that goes fast with reasonably available 
technology, I'd look into using a FPGA.

Xilinx Virtex-II gets to 840 megabits/sec if you use their DDR mode at the IO 
pins.  That means you have to generate 2 bits per clock.  That turns a single 
XOR gate into a bunch of them.  (I can't do the transformation on the fly, 
but it's not hard after you see it.  It's the same math that lets you process 
N bits at a time when computing a CRC.)

The Virtex-II-Pro includes RocketIO.  I haven't looked carefully.  A quick 
scan says up to 3 gigabits/second.  It has an option to bypass the 8B/10B 
encoding.  Again, the internal clocks won't go that fast so you will have to 
generate mutiple bits in parallel.



Are you just going to look at eye patterns with a scope?  Or do you want to 
check the bits?  For checking, look into self-synchronizing scramblers.  Lee 
and Messerschmitt: Digital Communication is what I use.

The idea is to send all 0s as a data pattern.  Run in through the scrambler.  
Feed that to your serial link.  That's the same bit pattern as you would get 
from a raw LFSR.  At the other end, run the received data through the 
descrambler.  Any 1 that comes out is an error.  The disadvantage of this 
approach is that for each single bit error on the link, you get the 
polynomial pattern out of the descrambler.  (A 1 bit error turns into a multi 
bit error.)  But it runs fast, and you don't need any extra circuitry to get 
things in sync.



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