[SI-LIST] Re: Building a PBRS generator?

  • From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
  • To: <steven@xxxxxxxxxxxxxxxxxxxx>, "SI-List" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 15 Mar 2004 17:57:06 -0800

Steve,
If I read this right, I don't think timing has anything to do with it.
This is a deterministic digital logic circuit and (assuming you do build
a legal digital circuit and meet setup and hold) will produce a
"reproducible pseudo-random" set
of bits.

I think the "reproducible" is important in the articles context as you want
to able to pre-load the
shift register with a starting value and get the same set of outputs so you
can reproduce an error
from the stream.


--------- all facts presented are the opinions of the author, unless wrong,
in which case they come from that guy on the list that no one likes.

---------


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Steven Kan
Sent: Monday, March 15, 2004 4:40 PM
To: SI-List
Subject: [SI-LIST] Building a PBRS generator?


After reading this article:

http://www.e-insite.net/ednmag/archives/1994/051294/10df3.htm

we're contemplating building up the circuit that is described here:

http://www.e-insite.net/ednmag/archives/1994/051294/graph/10df3fg1.htm

Does anyone here have experience building one of these? We'd like to build
as fast a circuit as we can using readily available parts, such as the ON
Semi MC100EL31, which will run up to 2.8 GHz.

The first question that comes to mind is the timing relationship between the
outputs of stages 18 and 23 and the input of the XOR gate. How does the
timing between these outputs and inputs affect the output stream? Does it
affect the "correctness" of the output, or does it just create a different
(but equally valid) PRBS?

Thanks!


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