[SI-LIST] Re: Buffer Delay
- From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
- To: <scubasnail@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 9 Apr 2003 08:55:28 -0700
This measurement really depends on how you are doing your timing
calculations. The important thing is that you are consistent such that you
do not double count (or under count) the total delay. Many data sheets give
internal buffer delay (or CLK to Q) delay and they specify the load and
conditions of that measurement. If you use that number for your timing
calculations, it is important to subtract that "Time to VM" portion of the
buffer delay from the entire path delay or you get double counting. You can
calculate this "Time to VM" part using simulation of just the buffer output
into the specified load. Some SI tools will do this for you automatically.
Others don't understand it at all. The same applies to timing tools.
I think if you look at the entire path in this light, you will see that the
problem can be approached in many ways. The important thing is to be
consistent.
regards,
jon
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Gil Gafni
Sent: Tuesday, April 08, 2003 6:38 PM
To: si-list@xxxxxxxxxxxxx
Cc: gil.gafni@xxxxxxxx
Subject: [SI-LIST] Buffer Delay
Greetings SI experts.
I wanted to address this forum with a buffer delay questions:
1. When a Buffer Delay analysis is performed, what kind of load should be
attached to the buffer
a. Pure Capacitor that represents the total load in pF of the
Package+lead+trace+any load in the way.
b. 'Real' load, e.g. the package's model, and W element for the TL?
2. What are the levels that we measure to?
a. Do we look at the Voh and Vol at the output of the buffer?
b. Do we look at the Vih and Vil of the target?
Thank you all in advance
Gil G
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