[SI-LIST] Buffer Delay
- From: "Gil Gafni" <scubasnail@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 8 Apr 2003 18:37:58 -0700
Greetings SI experts.
I wanted to address this forum with a buffer delay questions:
1. When a Buffer Delay analysis is performed, what kind of load should be
attached to the buffer
a. Pure Capacitor that represents the total load in pF of the
Package+lead+trace+any load in the way.
b. 'Real' load, e.g. the package's model, and W element for the TL?
2. What are the levels that we measure to?
a. Do we look at the Voh and Vol at the output of the buffer?
b. Do we look at the Vih and Vil of the target?
Thank you all in advance
Gil G
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