[SI-LIST] Re: Book - (Chassis - signal ground)

  • From: Neeraj Pendse <cnepsc@xxxxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx, Ken Cantrell <Ken.Cantrell@xxxxxxxxxxx>
  • Date: Fri, 22 Jun 2001 10:29:14 -0700

Hi Ken,

I am digressing from the main thread here, but i noticed you phrase "extend
your
power/ground planes far enough to absorb the fringing capacitance" and I wanted
to know more about that ...

Specifically: is there a general rule of how much the extension of plane (Which
is I guess measured from the edge of the edge trace) to avoid fringing
capacitance?

And from inductance standpoint also: how much should a plane extend in order
for the edge trace look like a microstrip ? Or in order to minimize loop
inductance of the trace returning through the plane?

Thanks and regards,

Neeraj Pendse
National Semiconductor Corp.
http://www.national.com

Ken Cantrell wrote:

> As a general rule, I no longer stitch boards (Montrose's unique
> contribution), but I do stitch chassis seams.  If you extend your
> power/ground planes far enough to absorb the fringing capacitance, and have
> minimized your unintentional radiators by correct layout, and have no
> intentional radiators, you won't need to stitch the board.  Of course, if
> that fails, I put the board stitches in.  Sometimes the magic works,
> sometimes it doesn't.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Padilla
> Sent: Friday, June 22, 2001 10:15 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Book - (Chassis - signal ground)
>
> Okay, Larry called so I must chime in here...
>
> I agree with chassis connections using the old lambda/20 rule but this
> isn't necessarily true for PCB stitiching as far as reducing EMI goes.
>
> By PCB stitching, I am assuming that (please correct my interpretation if I
> am wrong) you mean ground vias moving around the periphery of the PCB to
> help reach a Faraday cage effect, correct?  If so, read on....
>
> I have seen 3D simulations of multi-layer PCBs showing that energy bouncing
> back (i.e. reflecting off the periphery via, sign reversal) can cause
> problems as well by coupling the energy into other vias that help send it
> out the top/bottom of the board through traces and ICs.  So which is
> worse:  energy leaking out the edges of PCBs or energy leaking out the
> tops/bottoms of PCBs?  I haven't a clue and the simulation didn't provide
> answers to that question.  This is more food for thought.  I have to admit
> that seeing the energy bouncing around between planes on a PCB was
> disquieting but perhaps better there than leaking out the edge?
>
> Perhaps some discussion (and a new thread topic) will shed some light on
> ways to absorb energy at the periphery of PCBs?  I have heard of resistors
> being used at boards edges to try and accomplish this.
>
> What do I do in practice?  I still ask for ground via periphery stitching
> on all my boards (mostly high-density, hi-speed ethernet).
>
> ----->Chris
>
> Chris Padilla
> EMC Engineer
> Cisco Systems
>
> >If your board stitching and chassis connections are placed at a distance of
> >lambda/20 you reduce EMI, not enhance it.  The only time you can get away
> >with single point grounding is at very slow edge rates.  What you will do
> >with single point is increase your conducted emissions due to copper
> losses.
>
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