The below one day conference has been organized to deal with the problems
associated with interacting between these three areas.
Featured is keynote speaker, Sully Sullenberger of landing on the Hudson
fame.
Boards,Chips and Packaging:
Designing to Maximize Results
Computer History Museum, Mountain View, CA
October 13, 2015
Pre-registration $75.00 --Walk-up Registration $150.00
Today, chip designers craft their semiconductor products to meet
ever-increasing market demands for lower power, higher performance and lower
costs. While chips may meet system specifications, these complex designs
require even more attention at the packaging and board level to obtain the
full benefit of the chip design. Performance, power dissipation and form
factor challenges require a rechanneling of system design effort away from
merely implementing ever more-complex silicon solutions towards dealing with
complex applications from a system integration point of view. The rollout
of 3D, 2.5D and silicon interposers add yet another dimension.
The new model must incorporate tasks that had previously been accomplished
in silos and once held as separate functions. The creation of the system
solution now requires planning chip design with packaging and PCB layout to
create the optimal end application.
On October 13th, 2015, Semico will be gathering the industry's experts on
this topic to open a forum for discussion, insight, and collaboration to
enhance system-level design, performance and cost savings with first time
right solutions. Boards, Chips and Packaging: Designing to Maximize Results
is a must-attend event for board designers, system architects, chip
designers, package designers, program managers, and marketing executives
involved in the system-level ecosystem decisions. You will leave this event
with a better understanding of what you can do to get your company the
design wins that provide the highest performance and lowest power at the
least possible cost while minimizing respins.
The Semico IMPACT Conference "Designing to Maximize Results" will provide a
lineup of thought-provoking keynotes and enlightening panels. If you are a
board designer, system architect, an SoC designer or an ASIC design manager,
plan to attend this event on Tuesday, October 13, 2015 at the Computer
History Museum in Mountain View, California.
For more information contact:
Jim Feldhan
602-997-0337 Opt#1jimf@xxxxxxxxxx
Joanne Itow
602 997-0337 Opt #2
joannei@xxxxxxxxxx
Kella Knack
707-328-6865
kjspeedingedge@xxxxxx
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To unsubscribe from si-list:
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List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
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