[SI-LIST] "Bit Inversion" (e.g. DDR4) Simulation in HSPICE
- From: edward kowal <kowal_edward2007@xxxxxxxxxxx>
- To: SI LIST <si-list@xxxxxxxxxxxxx>
- Date: Mon, 21 Jul 2014 11:28:12 -0700
Due to the increasing popularity of the idea of "bit inversion" (by which I am
referring to a set of schemes that limit the number of simultaneously toggling
IOs via a parity requirement or similar), I have the need to generate these
kind of input vectors in HSPICE. Normally, for SSO I am just running PRBS's or
clock patterns, with each DQ uncorrelated to the other DQs. Can someone who
has done it get me pointed in the right direction about how to generate and
stimulate the IO banks with "bit inversion" compliant vectors?
Thanks,Ed
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