[SI-LIST] Re: Best PDS impedance for package damping
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: "'Larry Smith'" <Larry.Smith@xxxxxxx>,Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- Date: Fri, 13 Feb 2004 15:19:05 -0800
Cool! I think this is exactly what the system people need to know/model to
analyze the power distribution at system level.
As a one time chip head, however, this is not accurate enough for true die
power modeling as the power grid and on die capacitance is not a lumped
model as shown but a distributed one with localize loading and impedance
variation. After all, these mega giga processor will only see a single
version of the power ripple if your model is valid from different FUBs on
die. Unfortunately that's not true and what you've shown is just the loading
as presented by the die to the system (after filtering from the package).
There are techniques to measure/predict such localize impedance response on
die but I am afraid it is not as simple as you describe in your paper.
-----Original Message-----
From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
Sent: Friday, February 13, 2004 2:54 PM
To: Chris Cheng
Cc: steve weir; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Best PDS impedance for package damping
Chris - It is easier than you might think. You can measure the
impedance of a bare PCB with the packaged die mounted on it in the
normal way. The mounted chip behaves very similar to a mounted
decoupling capacitor and you can find the equivalent RLC of the series
circuit by curve fitting. Don't forget to subtract out the
capacitance of the PCB power planes and bias the power pins at their
normal operating voltage. This is the view from the PCB. The package
inductance and the chip capacitance are in series.
But what we really want to know is the view from perspective of the
chip terminals of the same components. But this time, the chip
capacitance is in parallel with the package inductance assuming that
the PCB PDS is a short circuit. So, just take the series components
and hook them up in a parallel fashion and you have a decent model for
what the chip sees when looking out. If the PCB PDS presents a little
resistance (hopefully at the target impedance) rather than a perfect
short, it just reduces the Q of the parallel RLC circuit.
The full details of this measurement are in a paper that is in the
SI-list documents that are maintained by Ray Anderson. Look up the
asme_2001.pdf paper.
http://www.si-list.org/files/published/sun/sun_papers.html
regards,
Larry Smith
Sun Microsystems
Chris Cheng wrote:
> Larry,
> How can you measure the inductance, capacitance and resistance profile as
> seen on die with a flip chip package ?
> Chris
>
> -----Original Message-----
> From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
> Sent: Friday, February 13, 2004 12:38 PM
> To: steve weir
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Best PDS impedance for package damping
>
> Another way to get this information is to measure it yourself. By
> mounting a processor or major ASIC on a bare fab, it is not difficult
> to find the equivalent inductance, capacitance and resistance of the
> component with a VNA S21 measurement. Istvan and I have documented
> the techniques for doing this in various papers. Be sure and bias the
> component with VDD because the capacitance across the device's power
> terminals changes greatly between zero bias and normal bias. By doing
> this, you have measured the chip/package resonance frequency
> (sometimes called cut-off) for the component on your board. This
> gives you great insight into what you need to do at the PCB level to
> provide power to the part. It also tells you what you cannot do (the
> frequency beyond which the packaged chip is on it's own).
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