Hello,
I am looking for implementation details for the behavioral Tx/Rx package models
at 16GT/s. Section 9.5.1.1 of the PCI Express Base Specification Revision 4.0
Version 0.7 from November 11, defines a topology with two parasitic
capacitances (CPIN and CPAD), one on each side of a differential t-line
element. The topology is depicted in Figure 9-38 and the values of parasitic
capacitances are given in Table 9-12. However there are no details about the
differential t-line element (impedance, length, complex propagation
coefficient, reflection coefficient) similar to those provided in the
IEEE802.3bj spec, Annex 93A, section 93A.1.2.3, Table 93A-3. Does somebody have
and can share this type of details?
Also it is specified (in the same section of the PCIe spec) that the package
models are included with the specification as design collateral. Can somebody
point me to the location from where I can download those models?
Thank you in advance,
Thank you,
Cristian
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
