[SI-LIST] Anomaly in Jedec DDR2 Derating Tables

  • From: Ralph A Wilson III <wilson@xxxxxxxxxxxxxxxxxx>
  • To: si-list <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 14 Oct 2008 12:14:56 -0500

In trying to set up some simpler timing rules for DDR2
batch analysis, I have been working to understand the
"engineering" behind the JEDEC derating tables for
setup / hold times due to slew rate.  I have run
across an anomaly in the hold time derating tables
that I'd like some feedback/comments on.
Although this anomaly appears (consistently) in
several of the tables, for discussion purposes here,
I'll choose the address slew rate derating table
(Table 46 of JEDEC Spec 79-2C).  To further narrow
the discussion, let's look only at the hold derating
column for a differential clock slew rate of 2.0V/ns
(Note: the impact to the derating due to clock slew is
linear and independent of the derating due to address
slew - the columns under 1.5V/ns and 1.0V/ns
are offset from 2.0V/ns by the formula 60 * (2-dV/dt),
(units of ps) where dV/dt is the differential slew rate
measured in V/ns).  We also need not go into the
non-monotonic and effective slew rate discussion.

So, simply looking at the hold time derating column for
the 2.0V/ns clock, we have:

Address    tIH
dV/dt    derating
(V/ns)     (ps)
4.00        94
3.50        89
3.00        83
2.50        75
2.00        45
1.50        21
1.00         0
0.90       -14
0.80       -31
0.70       -54
0.60       -83
0.50      -125
0.40      -188
0.30      -292
0.25      -375
0.20      -500
0.15      -708
0.10     -1125

The DDR2 timing specification states that the DDR2
address hold time should be measured from the clock
crossing to the address first crossing the input
DC voltage level.  The manufacturer provides us with
a required hold time (referred to as tDH in this
discussion), to which we add the derating based on
our address slew rate.

Doing a bit of reverse-engineering, the attached
drawing shows what appears to be going on.  The
hold time for a "real" device is measured at
VREF, not VIDC.  The hold time number the manufacture
provides assumes 1.0V/ns on the address lead.  This
provides the device with an additional 125 ps of
hold time as the address moves from the VIDC level
to the VREF level.  Hence, built in to the hold time
specified by the manufacturer is an assumption that
the device will have an additional 125 ps of hold time
beyond the number they provide.

If the slope of the address is greater than 1.0V/ns,
the time between VIDC and VREF is less than the assumed
125 ps and, hence, one must add some additional hold
time to that provided by the manufacturer (from the
derating tables).  If the slope is less than 1.0V/ns,
the time between VIDC and VREF is greater than the
assumed 125 ps, and, hence, one "gets some time back"
(the negative numbers in the derating table).

This theory holds (almost) perfectly.  Looking again
at the attached figure: the time a signal takes to
change from VIDC to VREF is (VIDC - VREF) / dV/dt.
For all DDR2, "VIDC - VREF" is 125mV.  For 1.0V/ns
slew rate, this time is 125 ps.  Adjusting the slew
rates to intersect at VREF, as shown in the figure, the
difference between the VIDC crossing of the actual
signal and the VIDC crossing of the assumed 1V/ns
signal (delta tDH in the figure) is the value we
need to derate the hold time.

A little trig and algebra provides us with the following
equation for hold time derating:

delta tDH = (VIDC - VREF)*(1 - dt/dV)
or, delta tDH = 125 * (1 - dt/dV)
where the answer is in ps, and dt/dV is the inverse
of the address slew rate in V/ns.

Now comes the anomaly.  Generating hold time deratings
using this method, gives us the following table:

Address    tIH
dV/dt    derating
(V/ns)     (ps)
4.00        94
3.50        89
3.00        83
2.50        75
2.00        62  <====
1.50        42  <====
1.00         0
0.90       -14
0.80       -31
0.70       -54
0.60       -83
0.50      -125
0.40      -188
0.30      -292
0.25      -375
0.20      -500
0.15      -708
0.10     -1125

Close examination will show this exactly matches the
JEDEC table with two exceptions - those at an address
slew rate of 2.0 V/ns and 1.5V/ns.  At 2.0V/ns my
calculation says we need to derate the hold time by
62 ps, however the JEDEC table says do derate only 45.
Similary for 1.5V/ns (42 ps vs. the JEDEC spec of 21).
Again, this is consistent for all hold rates in all
tables (both address and data, across all DDR2 clock
frequency rates, and across all clock slew rates).

So, my question is:

*) Is my theory/analysis full of B.S., and it is only
coincidental that the calculations come as close as they do.

*) Is there an unintended error in the JEDEC derating
numbers?

*) This theory/analysis is correct, and the calculations
are correct, but, for reasons unknown, JEDEC decided
to "adjust" these two numbers with some other fudge factor.

Anyone out there recall any JEDEC committee discussion
on this?  Other comments, opinions, insight?

Thanks!
Ralph Wilson
Alcatel-Lucent



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