[SI-LIST] Re: Analog & Digital Grounds
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Traa, Boris" <boris.traa@xxxxxxxxxxx>
- Date: Mon, 12 Oct 2009 03:10:28 -0700
Mysterious impedances in the reference are an invitation to nasty
problems. That said, suppose you have a 24bit A/D converter, 5V FS.
Each LSB is a fraction of a uV. It will take only a small amount of
induced or DC current to develop multiple LSBs of noise in the common.
In cases like this, the required lateral separation of digital traces to
prevent excessive induced EMFs could easily be prohibitive. Proper
moating and fencing would allow practical packaging while meeting the
noise requirements.
Steve.
Traa, Boris wrote:
> For what reasons should you separate analog and digital ground? If an IC is
> provided with separate grounds on package and die and you measure the
> impedance between these ground at the balls/pins you may come up with a low
> impedance for the concerned frequencies due to the various capacitive
> coupling paths. In my opinion it is better to have a defined short circuit
> than a mysterious impedance between ground domains.
>
> Kind regards
> Boris Traa
> System design engineer EMC
>
> It's the currents that make circuits work or fail.
>
> Philips Applied Technologies/EMC center
> Room 2.020
> High Tech Campus 26
> 5656AE Eindhoven, The Netherlands
> Tel: ++ 31 40 27 43766
> Fax: ++ 31 40 27 42224
> E-mail: boris.traa@xxxxxxxxxxx
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Lee Ritchey
> Sent: 2009 Oct 12 2:16 AM
> To: Chris Adam; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Analog & Digital Grounds
>
> Chris,
>
> Good question. I've never separated analog and digital grounds. That may
> sound pretty strong, but it is true for 2000+ designs.
>
> I think the recommendation to separate analog and digital ground stems from
> the fact that mixed signal parts often are equipped with both type of
> ground pins. This is not done so you have to design two separate grounds
> in the PCB, but rather so the two internal circuits don't share the same
> ground path out of the package. This is vital for A/D and D/A converters
> and assorted video circuits. If not done, the "ground bounce" when the
> digital circuits switch is coupled into the analog circuits which usually
> are working with very small signals or small changes in signal value. A
> ground bounce spike that would not disturb a digital circuit can totally
> disable the analog function.
>
> Sometimes the same issue applies to Vdd.
>
> Lee Ritchey
>
>
>
>> [Original Message]
>> From: Chris Adam <chris.adamsipi@xxxxxxxxx>
>> To: <si-list@xxxxxxxxxxxxx>
>> Date: 10/9/2009 3:53:48 PM
>> Subject: [SI-LIST] Re: Analog & Digital Grounds
>>
>> Thanks Lee and all those who offered valuable suggestions offline.
>> When do you really care to separate analog and digital grounds ? I see
>>
> some
>
>> transceiver vendors recommend splitting the grounds while others don't.
>>
>> Thanks,
>> - Chris.
>>
>>
>>
>>
>> On Fri, Oct 9, 2009 at 8:29 AM, Lee Ritchey
>>
> <leeritchey@xxxxxxxxxxxxx>wrote:
>
>>> First of all, there is no sacred rule that analog ground and digital
>>>
> ground
>
>>> must be separate. Who knows where that came from. Use only one ground
>>> plane and manage the current flows so that digital ground currents don't
>>> flow under the area where the analog circuits are situated. It's pretty
>>> easy to do in most cases.
>>>
>>>
>>>
>>>
>>>> [Original Message]
>>>> From: Chris Adam <chris.adamsipi@xxxxxxxxx>
>>>> To: <si-list@xxxxxxxxxxxxx>
>>>> Date: 10/8/2009 5:47:35 PM
>>>> Subject: [SI-LIST] Analog & Digital Grounds
>>>>
>>>>
>>> > I am working on a PCB design where number of layers is limited to 4
>>>
> to
>
>>>> reduce cost. As opposed to the regular 'sacred rule', analog and
>>>>
> digital
>
>>>> grounds are not separated though the respective VDDs are isolated. I
>>>>
> am
>
>>>> particularly concerned that the merged ground is also a return path
>>>>
> for
>
>>>> DDR2 signals. I would like to see how much noise does this ground
>>>>
>>> merging
>>>
>>>> will introduce in sensitive power supply nodes such as for PLL and
>>>>
> CDR.
>
>>> What
>>>
>>>> would be the appropriate simulation set up for this ? I am thinking of
>>>> multiport s-parameters, transfer impedance etc. I would appreciate if
>>>>
>>> any
>>>
>>>> one shares his/her experience, thoughts and insights in this type of
>>>> analysis.
>>>>
>>>> - Chris
>>>>
>>>>
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>>>
>>>
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