[SI-LIST] Re: Analog & Digital Grounds

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: Gene Glick <gglick@xxxxxxxxxxxx>
  • Date: Thu, 15 Oct 2009 16:56:00 -0700

Gene, yes that is the general idea.  Currents follow an expanding path 
at lower densities as the frequency goes down / time scale goes up.  In 
your example, moating would prevent I*R drops from low frequency 
components of the terminator current from polluting the analog common.  
You could get the same effect with a virtual moat by choosing where the 
analog ground ties to the rest of the system.  The age old advice is to 
follow the currents.  Burn Lenz into your psyche and that becomes easier.

Steve
Gene Glick wrote:
> steve weir wrote:
>   
>> Gene, think Lenz.  Be Lenz.  
>>   
>>     
> Ugh, I barely remember what class Lenz's law was taught in :) Thanks, 
> though.
>
> Hey, I got to thinking about this further and put together a simulation 
> experiment.  Hopefully, this simplified setup helps to explain a few 
> things on my mind.  Here's what I did:
>
> I wanted a simple circuit that would give me some idea about where the 
> return currents flow in a ground plane.  Rather than go the field solver 
> route, I chose to use LTSpice and mock up something that hopefully gives 
> insight.  The basic premise is to glean some understanding on where the 
> currents flow.  So, I made a surface trace modeled as R-L and a 
> ground-plane modeled as two R-L circuits.  There's a load that can be a 
> resistor or capacitor.  The 2 return lines comprise the ground plane, 
> and the source trace is coupled to one of the return lines and not 
> coupled to the other. 
>
> This simple view is meant to see how much current flows in each portion. 
> A real plane would be made up of infinite number of these section.  The 
> ones closest to the signal trace have the tightest coupling, those 
> farther away have less, and eventually no coupling if I go far enough 
> away.  So, I modeled the 2 extremes.
>
> Have a look:
> Circuit diagram is here:
> http://www.geocities.com/fazool1_2000/si-list/returnCurrentTest.pdf
>
> Hopefully the output file names indicate how the circuit was setup:
> http://www.geocities.com/fazool1_2000/si-list/sinewave-dcLoad-noCoupling.pdf
> http://www.geocities.com/fazool1_2000/si-list/sinewave-dcLoad-tightCoupling.pdf
> http://www.geocities.com/fazool1_2000/si-list/squareWave-acLoad-noCoupling-sourceTerminated.pdf
> http://www.geocities.com/fazool1_2000/si-list/squareWave-acLoad-tightCoupling-noTermination.pdf
> http://www.geocities.com/fazool1_2000/si-list/squareWave-acLoad-tightCoupling-sourceTerminated.pdf
>
> For you LTSpice folks, here's the file if you want to play around with it:
> http://www.geocities.com/fazool1_2000/si-list/returnCurrentTest.zip
>
>
> Some conclusions:
> 1. When tightly coupling the signal trace to the return plane the return 
> current flows *mostly* in the tightly coupled trace, but  *some* flows 
> in the non-coupled.  Therefore, it may be important to be cautious on 
> the pcb placement and routing such that the returns currents that take 
> the paths not directly underneath the trace, don't affect sensitive 
> analog circuits, for example.
>
> 2. When not tightly coupled, the return current simply shares the all 
> the return paths.
>
> 3. Not shown, but simulated a DC load, resistor, with square wave 
> source.  When tightly coupled to the ground plane, the non-coupled trace 
> still has some portion of the DC signal with a small AC portion riding 
> on it. Again, a problem for sensitive circuits I think. This one changes 
> my perspective on end-termination since it can create a DC return 
> current where it may not be welcome.
>
>
>
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