[SI-LIST] Allowed Crosstalk on DDR2 Strobe (DQS)

  • From: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 02 Feb 2009 17:03:45 +0200

Hello all,
 
I would like to ask if there is any specification which claims the
amount of allowed crosstalk on the (single-ended or differential) DQS of
the DDR2 interface.
 
As I understand it, assuming the signal is generally well behaved (no
significant overshoot or ringing and is monotonic throughout its
threshold region), then the crucial thing is what happens if and when a
noise from another signal happens to ride on top of the DQS signal -at
the time of its threshold transfer region. This event may cause the
signal to be non-monotonic and this seems to me the worst threat to the
signal functioning.
 
But what level of crosstalk will cause such non-monotonicity to disrupt
the signal functionality? At principle, any level should be dis-allowed,
even 1mV! But this seems to be un-reasonable, as on embedded
applications the routing is so dense this isn't an achievable goal.
 
Could anyone answer this question - from the DDR2 specification or from
any electrical reasoning?
 
Thanks in advance
 
Itzhak Hirshtal

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