[SI-LIST] Adjacent Power Plane Noise Coupling
- From: ndempshe@xxxxxxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 17 Dec 2004 17:14:24 -0500 (EST)
Hi SI LIST,
I have a question about power to power plane spacing in designing a stackup and
whether I should be concerned about noise coupling from one plane to another.
I have searched the archives on this topic and have only found discussions
of spacing between split power planes on the same layer.
We are designing a large, dense, double sided board, multiple 1100+ ball FPGAs
at 225MHZ+, SPI4, DDR, CSIX, PCI etc. - the normal alphabet soup.
There are over two dozen different voltages required for these multiple devices
and interfaces. Added to this are red-black data security boundaries which
should not be crossed.
These voltages have been distributed across six power planes, not including VTT
DDR miniplanes on the top and bottom of the PWB.
In designing the stackup I am trying to maintain ground referencing as much as
possible for the signals and am therefore creating power ground pairs toward
the
center of the stack with GND SIG SIG GND planes away from the center. Distance
between layers is 3.5-4 mils..
In order to reduce the number of power and ground plane pairs and have
additional routing layers I would like to cheat a bit, if possible, and create
the following stackup in the center of the board:
PWR1
PWR2
GND4
PWR3
PWR4
GND5
PWR5
PWR6
PWR1 and PWR6 contain high speed interface IOs (2.5V TTL and CSIX) and only
traces associated with these voltages will be run adjacent to them.
For this particular design power plane coupling that is too much could be
analyzed on 3 levels that I can think of:
1. Red-black data security issues: Anyone monitoring accessible black
interfaces
picking up red - unencrypted - information. There is no overlap between red and
black voltage planes and there is a gap between them. I am assuming that this
should not be a problem. There will probably be a picket fence between them.
2. There are 0.75 volt CSIX reference voltages on one plane (PWR3) adjacent to
3.3v I/O voltage on the neighboring plane (PWR4). Coupling into a reference
voltage to create erroneous data.
3. There are core voltage planes (PWR2) adjacent to 2.5v I/O. Coupling between
these two voltages.
Is there a way to estimate the amount of coupling (5%, 10% ?) between adjacent
power planes versus distance or isn't this really an issue?
Much Thanks In Advance,
Ned Dempsher
Senior Member Engineering Staff
L-3 Communications
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