[SI-LIST] Re: About the DDR2 Data Tim ing Budget Calculation

  • From: "Peterson, James F \(FL51\)" <james.f.peterson@xxxxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 20 Apr 2006 06:31:26 -0500

In response to both of these follow up questions regarding accounting =
for pcb skew in DDR2 designs (see Jeffery's also): I must confess to =
being a DDR SDRAM designer who has tracked with interest the differences =
and improvements in DDR2 (but no DDR2 designs....yet), so I will look =
for someone more qualified to answer these good questions.

Jim=20
Honeywell=20

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of dayedit@xxxxxxx
Sent: Wednesday, April 19, 2006 11:14 PM
Subject: [SI-LIST] Re: About the DDR2 Data Tim ing Budget Calculation

HI Jim,
Also I have the similar problem with Jeffrey in calculating DDR2 timing, =
and most time, when considering crosstalk and ISI effects, I get a =
negative timing margin. So I wonder whether I double calculating some =
effects.We can use derating table to calculate setup/hold time when =
differential DQS crossing point Vref(dc) is defined zero, we =
needn=A1=AFt consider skew caused by Vil and Vih because setup/hold time =
definitions include this effects, but when differential DQS crossing =
point isn=A1=AFt zero, according to JEDEC 792B, VIX (ac) ac differential =
cross point voltage can be between 0.5 * VDDQ - 0.175V to 0.5 * VDDQ + =
0.175V, it seems that derating table didn=A1=AFt include this effects, =
it just reference Vref as a constant, so skew caused by Vref still is =
not considered, especially for single ended DQS( here I regard Vref as =
variable between Vil and Vih). To get a positive margin, I hope I=A1=AFm =
wrong in understanding the parameters.B.R.Greg
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