[SI-LIST] AW: Re: relationship between reeceiver jitter transfer and jitter tolerance
- From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- To: "enwag2002@xxxxxxxxx" <enwag2002@xxxxxxxxx>, "tkjeon@xxxxxxxxxxx" <tkjeon@xxxxxxxxxxx>, "chris.cheng@xxxxxx" <chris.cheng@xxxxxx>, mark <mark@xxxxxxxxxxxxxx>
- Date: Tue, 31 Jul 2012 14:40:03 +0000
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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von an wage
Gesendet: Dienstag, 31. Juli 2012 16:36
An: tkjeon@xxxxxxxxxxx; chris.cheng@xxxxxx; mark
Cc: si-list
Betreff: [SI-LIST] Re: relationship between reeceiver jitter transfer and
jitter tolerance
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From: T.K. Jeon <tkjeon@xxxxxxxxxxx>
To: "chris.cheng@xxxxxx" <chris.cheng@xxxxxx>; mark <mark@xxxxxxxxxxxxxx>
Cc: si-list <si-list@xxxxxxxxxxxxx>
Sent: Monday, July 30, 2012 3:40 PM
Subject: [SI-LIST] Re: relationship between reeceiver jitter transfer and
jitter tolerance
Considering all signal impairments including ISI, let's say BER starts to
increase when the phase error to Rx is bigger than K unit interval.(K is a
constant).
Since the error free condition is Jit_in - Jit_out < K and the jitter transfer
fucntion(Jit_out/Jit_in) of CDR is H(s), Jit_in, the input jitter tha Rx can be
tolerable, is extracted like following.
Jit_in - Jit_out = Jit_in - Jin_in*H(s) = K ---> Jit_in = K/(1-H(s))
Therefore, Jit_in has two poles at the origin and two zeros. As the result, the
jitter tolerance will show 40dB/dec at the very low frequecy and start to fall
at a rate of 20dB/dec at the first zero and intersect at the second zero, which
is the same w_-3db as the one from the jitter transfer function, H(s).
Best Regards,
TK
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Cheng, Chris
Sent: Saturday, July 28, 2012 1:44 PM
To: mark
Cc: si-list
Subject: [SI-LIST] Re: relationship between reeceiver jitter transfer and
jitter tolerance
Mark,
I should clarify my original statement. The pattern is sent by a BERT
instrument, at the receiver pin with minimal ISI. The motivation for this
exercise is that it is almost impossible to put high speed device to loop back
mode and observe jitter transfer. I am hoping the "jitter tolerance" described
can be an alternative for it.
Chris
Sent from my iPad
On Jul 28, 2012, at 11:00 AM, "mark" <mark@xxxxxxxxxxxxxx> wrote:
> Chris,
> When a data pattern is introduced to jitter tolerance then ISI is
> introduced as a term. The ISI may be sufficient to close the EYE
> vertically and also close the EYE horizontally. Receive equalization
> attempts to recover some of the loss due to ISI. The ISI that is not
> compensated for has been called non-compensable jitter in some
> circles. Lets say we have 20% UI on non-compensable jitter.
>
> Then to your question:
> a) if the jitter tolerance is greater than 1 UI is the jitter transfer
> equal to 1?
> No. for two reasons.
> 1) jitter tolerance consists of the ISI + sinusoidal jitter. The
> jitter tolerance at high frequency is limited by the closure due to
> ISI and the receive CDR circuit design. Say the receive circuit needs
> 30% opening and the ISI due to your CJTPAT is 20%. The high frequency
> jitter tolerance is ~ 50%. So sinusoidally modulated jitter up to 50%
> can be applied at high frequencies. When the
> 2) even with no ISI or circuit related jitter tolerance, the pure
> jitter tolerance of an ideal CDR is +- 0.5 UI at high frequency, Then
> as a the CDR tracks the incoming jitter the tolerance can increase.
> Also the dynamics 2nd order or 3rd order behavior can make the jitter
> tolerance actually decease initially before increasing.
>
> So in total the high frequency jitter tolerance is < 1 UI due to ISI
> and circuit reasons, and the point at which jitter tolerance grows to
> 1 UI is a function of the transfer function shape and the starting
> point at high frequency. A receiver with 0.1UI high frequency
> tolerance will have a different frequency of modulation for 1 UI
> tolerance for the same CDR TF as a receiver with 0.8UI high frequency
> tolerance.
>
> For b)
> Jitter tolerance is a grade of exceeding a threshold. The phase error
> is the input jitter*(1-jitter transfer). So The equation is closer to
> jitter tolerance = input_jitter*(1-transfer) - "constant"
>
>
> This is true for all frequencies and amplitudes of jitter.
>
> Best Regards,
> Mark
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Cheng, Chris
> Sent: Friday, July 27, 2012 7:08 PM
> To: si-list
> Subject: [SI-LIST] relationship between reeceiver jitter transfer and
> jitter tolerance
>
> Hi there,
>
> I think the classical definition of jitter transfer is related to how
> much jitter at the input of receiver get transfered to the output of
> the receiver.
> The classical definition of jitter tolerance is related to how much
> input reference clock jitter is acceptable for a given bit error rate.
> What if I modify slightly the definition of jitter tolerance to the
> receiver as, how much jitter can be applied to the input (instead of
> reference clock) before you have a receiver error.
> A practical way of doing the above is to send a known pattern such as
> CJTPAT to a receiver and then modulate it with a fixed frequency
> jitter. The minimum jitter amplitude that will trigger errors will be
> defined as jitter tolerance as above.
> So my question is, if one does the experiment above and plot out the
> jitter tolerance vs. frequency. How does that receiver jitter
> tolerance related to the receiver transfer curve ?
> Can I interpret the receiver jitter tolerance and transfer relationship as:
> a) For jitter tolerance > UI, the jitter transfer is 1 or unity
> b) For jitter tolerance < UI, the jitter transfer = UI - jitter
> tolerance - "some constant"
> where "some constant" is probably related to the setup and hold
> requirements of the receiver
>
> Thanks in advanced,
>
> Chris Cheng
> Distinguished Technologist , Electrical Hewlett-Packard Company
>
> +1 510 413 5977 / Tel
> chris.cheng@xxxxxx / Email
> 4209 Technology Dr
> Fremont, CA 94538
> USA
>
>
>
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Other related posts:
- » [SI-LIST] AW: Re: relationship between reeceiver jitter transfer and jitter tolerance - Havermann, Gert