[SI-LIST] Re: AW: Re: Reference layers for high speed diff pairs
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Vinu Arumugham <vinu@xxxxxxxxx>
- Date: Wed, 23 Jan 2013 21:32:28 -0500
On Wed, Jan 23, 2013 at 8:08 PM, Vinu Arumugham <vinu@xxxxxxxxx> wrote:
> Scott,
>
> To clarify, by "ground is significantly quieter than any other power
> reference rails.", I believe you are referring to the following
> measurements:
>
> (i) At location x1,y1 near a signal via, measure noise between two ground
> planes.
> (ii) At location x2,y2 near a signal via, measure noise between a power
> and a ground plane.
>
> Noise (ii) likely to be > noise (i). The signal going through the via
> transitioning between those two reference planes will be affected by the
> noise that was measured.
>
Yes! And by reciprocity the signal going through the via will inject noise
into the planes. The conclusion is a generality and assumes that in the
local vicinity that two ground planes are better stitched that a power
plane (which may not be stitched at all.)
>
> Going back to Jeff's cases:
>
> "(a) Transmitters and receivers are solely VDDQ referenced and the PCB
> is solely VDDQ referenced
> (b) Transmitters and receivers are solely VDDQ referenced but the PCB is
> solely "GND" referenced"
>
> (a) has no transition but (b) does. So the noise measured in (ii) does not
> affect the signal in case (a).
>
> Hence my assertion that (a) is better than (b). Do you agree?
>
In both cases there will be a noise differential between VDDQ and GND at
the Tx and Rx. For the second case there will be additional noise
differentials as the signal embarks and disembarks to GND from/to VDDQ at
the PCB/PKG boundary. But, the package to PCB transition needs to support
the transition.
If we're going from VDDQ to VDDQ, then there need to be VDDQ balls and vias
that connect the package to the board, in order to support a smooth
transition. If we're going from VDDQ to GND there need to be VDDQ and GND
balls and vias to support a smooth transition. Crosstalk at the transition
will depend on the placement of the Balls/vias w.r.t. the location of the
signal balls/vias. Actual performance under simultaneous switching
conditions will depend on where the VDDQ and GND balls are located. It is
possible to engineer a clean VDDQ referenced signalling interface, but it
requires additional VDDQ balls to meet the crosstalk performance of a GND
referenced signalling interface.
So, my answer is ... wait for it ... it depends ... on where the VDDQ balls
are. If the package has VDDQ balls in the right places, the fully VDDQ
referenced interconnect will have lower noise. If not, then we're playing
Wack-A-Mole.
If I had to compromise, I'd go for one GND plane and one VDDQ plane with
balanced stripline. That way the propensity of GND balls and vias will
support all the necessary mode conversions.
> Thanks,
> Vinu
>
>
>
> On 01/23/2013 03:34 PM, Scott McMorrow wrote:
>
> Vinu
>
> You are absolutely correct. At any spatial region within a PCB you can
> make relative measurements between any two points. A measurement between a
> ground plane and two different Vdd planes will yield meaningful results.
> In addition, measurements between two ground planes at the same X-Y
> location are also meaningful. Hybrid solvers like Ansys SIwave are capable
> of making these measurements in full package and board simulations. If
> anyone is really interested on the implications of Pwr/Gnd signal
> referencing and transition of signals through vias, a tool like this
> is indispensable. If you care to take more time, memory and CPU resources,
> it's also possible to use HFSS to validate these same results for
> well-designed test cases. I've been doing this for last few years,
> comparing the results to measurements from DC to 40 GHz for several of my
> customers, enabling them to better engineer their interconnect.
>
> The reason that I prefer ground referencing is that in many systems,
> ground is significantly quieter than any other power reference rails. The
> reason for this is that there are generally more ground planes, and those
> planes are stitched by many more vias than the power planes. (For power
> planes to be "stitched" requires that there is at least a pair of power
> planes at the same voltage that can be tied together with vias to suppress
> full-wave parallel plate mode propagation. At 10G data rates and below, it
> is possible to make dual-referenced packages and PCBs robust, with some
> extra engineering when compared to Gnd/Gnd referenced stripline. But as the
> data rate rises, and the frequency spectrum of the data stream increases,
> second order full-wave effects start to become prominent. Ignore these
> now ... deal with the results during test or production.
>
> regards,
>
> Scott
>
>
>
> On Wed, Jan 23, 2013 at 6:00 PM, Vinu Arumugham <vinu@xxxxxxxxx> wrote:
>
>> Measuring VDDQ with respect to a local ground is perfectly valid. It can
>> tell you if say VDDQ1 is quieter than VDDQ2 with respect to that ground.
>> My comments refer to "is GND quieter than VDDQ?".
>>
>> Thanks,
>> Vinu
>>
>> On 01/17/2013 02:24 PM, Loyer, Jeff wrote:
>> > To me, the quieter plane will be the one with less noise when measured
>> relative to the nearby ground (reference). While it's true that the
>> "ground" at the transmitter may not be the same "ground" as the receiver
>> (or other locations), at the receiver the critical parameter will be the
>> noise relative to the ground (reference) at the receiver. I'm not sure why
>> measuring VDDQ with respect to a local ground (reference) is invalid. To
>> me, choosing a third node introduces error since that node will probably be
>> physically and/or electrically isolated from what I'm concerned with -
>> noise relative to local ground (reference).
>> >
>> > Jeff Loyer
>> >
>> >
>> > -----Original Message-----
>> > From: Vinu Arumugham [mailto:vinu@xxxxxxxxx]
>> > Sent: Wednesday, January 16, 2013 1:30 PM
>> > To: Loyer, Jeff
>> > Cc: si-list@xxxxxxxxxxxxx
>> > Subject: Re: [SI-LIST] Re: AW: Re: Reference layers for high speed diff
>> pairs
>> >
>> > "Thus, it doesn't matter which plane you choose to reference your
>> signal to - the quieter one gives more margins."
>> >
>> > How does one determine which plane, VDDQ or GND is quieter? We usually
>> measure VDDQ w.r.t GND and that will not provide the answer. We have to
>> choose a third node as reference to answer that question. The answer will
>> also depend on the choice of that reference node. Then there is the
>> question of whether signals transmitted referenced to VDDQ or GND are
>> affected at all by the noise measured w.r.t that reference node.
>> >
>> > In other words, for a signal that is going to reference VDDQ or GND,
>> the question of which one is quieter seems meaningless.
>> >
>> > Thanks,
>> > Vinu
>> >
>> >
>> >
>> > On 01/16/2013 08:28 AM, Loyer, Jeff wrote:
>> >> Actually what I wrote is what I intended. To my thinking, the signals
>> are best when they are "quiet" with respect to the "ground" that the
>> transmitter and/or the receiver is using as its reference for all voltages.
>> I believe that the reference plane with the least amount of noise relative
>> to that would be the "ground" planes in the Tx and Rx. I personally can
>> justify VDDQ referencing in packages to save layers and/or improve Power
>> Integrity (which in turn improves signal integrity, often dramatically),
>> but I'm not convinced it has inherent advantages in how the signal is
>> propagated, by itself. I would expect referencing a trace to VDDQ to be
>> inferior to referencing that trace to GND if everything else is kept
>> identical.
>> >>
>> >> The drawings that I see calling for VDDQ referencing as an advantage
>> treat current as a directional entity - as arrows, with "transmission line"
>> current going in one direction and the "return" current going the other.
>> But I don't think this is the correct model for AC energy travelling down
>> a trace.
>> >>
>> >> The experiments that I've seen where VDDQ referencing is shown to be
>> superior to GND referencing have all had inherent Power Integrity
>> advantages, thus it's not an apples-to-apples comparison of just the
>> referencing scheme. I believe that, if you could build 2 scenarios where
>> the power distribution network were identical and the only change was what
>> plane (GND vs. VDDQ) the signals were referenced to, the GND referencing
>> scheme would be quieter.
>> >>
>> >> To be clear, this is a little different than the scenario where you
>> change reference planes. In my experience in server designs, there is
>> virtually zero impedance between VDDQ and GND planes, even on a bare board.
>> Shooting a TDR between them, you see a dead short (unless you wait a very
>> long time in which case you'll see the classic charging of a capacitor).
>> Thus, it doesn't matter which plane you choose to reference your signal to
>> - the quieter one gives more margins. Thus, (b) is superior to (a). On
>> the other hand, I can imagine a scenario where there is finite impedance
>> between the two planes (thick, 4 layer stackup) and changes in the
>> reference plane could have profound impact due to that discontinuity;
>> perhaps in this case (a) is superior to (b), though I personally haven't
>> seen a case study proving this to be true.
>> >>
>> >> Jeff Loyer
>> >>
>> >>
>> >> -----Original Message-----
>> >> From: si-list-bounce@xxxxxxxxxxxxx
>> >> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Vinu Arumugham
>> >> Sent: Friday, January 11, 2013 9:58 AM
>> >> To: si-list@xxxxxxxxxxxxx
>> >> Subject: [SI-LIST] Re: AW: Re: Reference layers for high speed diff
>> >> pairs
>> >>
>> >> Jeff,
>> >>
>> >> "For instance, I don't see that scenario (a) would ever be superior to
>> (b)." Did you mean that or is it flipped?
>> >>
>> >> I expect (a) to be better than (b). VDDQ planes are noisy w.r.t GND.
>> You can also view it as GND planes being noisy w.r.t VDDQ.
>> >> So solely VDDQ referenced is no different than solely GND referenced.
>> Switching between VDDQ and GND reference can be a problem. Referencing both
>> VDDQ and GND planes in the presence of VDDQ/GND noise can also be a problem.
>> >>
>> >> Thanks,
>> >> Vinu
>> >>
>> >>
>> >>
>> >> On 01/11/2013 08:01 AM, Loyer, Jeff wrote:
>> >>> Shchif touches on one of the (to me) most troubling aspects of this
>> issue when it is in the "system" realm. From my experience and the
>> discussions we've had in this forum, I'm not sure any measurements except
>> for margining would indicate whether a problem existed. Imagine two
>> scenarios:
>> >>> (a) Transmitters and receivers are solely VDDQ referenced and the PCB
>> >>> is solely VDDQ referenced
>> >>> (b) Transmitters and receivers are solely VDDQ referenced but the PCB
>> is solely "GND" referenced
>> >>> (you can flip the referencing scheme if you like such that the Tx
>> >>> and Rx are GND referenced and the PCB is GND or VDDQ referenced and
>> have the same discussion) The key aspect is that the Tx and Rx are
>> identical for both scenarios, but I want to distinguish between the two
>> PCBs w/ passive measurements. One is "good", the other is "bad".
>> >>>
>> >>> >From my experience, the s-parameters of the 2 PCB's may be virtually
>> identical (even bare boards w/o any decoupling) - interplane capacitance
>> between VDDQ and GND make them indistinguishable. How do you predict which
>> scenario will perform better?
>> >>>
>> >>> My experience also agrees with Scott's, that noisy VDDQ planes (vias,
>> balls) are bad things which should be avoided, but I don't see it being
>> related to any Tx or Rx referencing scheme; it seems to be a separate issue
>> (a noisy plane or trace adjacent to a victim is a bad thing). For
>> instance, I don't see that scenario (a) would ever be superior to (b). If
>> there is some case study which explains otherwise, please point me to it.
>> >>>
>> >>> Regarding the original question, I've had experience with
>> differential pairs that are virtually immune to common-mode noise; I
>> couldn't break them by injecting common-mode noise on the pair no matter
>> how hard I tried. I've also had experience with differential pairs (a
>> clock signal particularly) in which common-mode noise broke that link.
>> Yes, theoretically they are much less susceptible to common-mode noise
>> (than single-ended signals), but they are not completely immune. For
>> instance, any mismatch between the pair turns common-mode noise into
>> differential noise.
>> >>>
>> >>> Thanks,
>> >>> Jeff Loyer
>> >>>
>> >>>
>> >>> -----Original Message-----
>> >>> From: si-list-bounce@xxxxxxxxxxxxx
>> >>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Havermann, Gert
>> >>> Sent: Thursday, January 10, 2013 11:59 PM
>> >>> To: shchifwork@xxxxxxxxx; si-list@xxxxxxxxxxxxx
>> >>> Subject: [SI-LIST] AW: Re: Reference layers for high speed diff pairs
>> >>>
>> >>> Shchif,
>> >>> The 3D Field solver calculates the behavior oft he complete structure
>> including the ref-planes. If the return current is forced to take a
>> "detour" across coupling caps or far away vias, then this will directly
>> influence the s-parameters of the signal path. If multiple return currents
>> all use a single via, then this will increase crosstalk.....
>> >>>
>> >>> Many effects are hard or impossible to predict just by looking at the
>> design, and this is especially true for people without long experience in
>> Simulation, testing and verifying high speed stuff. Scott is one of these
>> highly experienced SI-Gurus, and he warns you to follow option #2 for good
>> reason. And I second that.
>> >>>
>> >>> BR
>> >>> Gert
>> >>>
>> >>>
>> >>> ----------------------------------------
>> >>> Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
>> >>> Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.:
>> >>> HRB 8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm.
>> >>> Edgar-Peter Düning, Dipl.-Ing. Torsten Ratzmann, Dr.-Ing. Alexander
>> >>> Rost
>> >>>
>> >>> -----Ursprüngliche Nachricht-----
>> >>> Von: si-list-bounce@xxxxxxxxxxxxx
>> >>> [mailto:si-list-bounce@xxxxxxxxxxxxx] Im Auftrag von Ilan Wolff
>> >>> Gesendet: Donnerstag, 10. Januar 2013 21:16
>> >>> An: si-list@xxxxxxxxxxxxx
>> >>> Betreff: [SI-LIST] Re: Reference layers for high speed diff pairs
>> >>>
>> >>> Hi Scott,
>> >>>
>> >>> Thanks for your feedback.
>> >>> I must admit ther's point in your reply regarding the 3D solver that
>> I dont quite follow.
>> >>> (I might be exposing my ignorance in the next few lines, but I guess
>> >>> this is the way to learn.)
>> >>>
>> >>> Lets say I go for the 1 GND & 1 power plane option (#2), and that on
>> the system level PCB the same reference plane scheme is used.
>> >>> 1. How would the solver be
>> >>> able to differentiate between the two types of planes?
>> >>> 2. Up to now Ive seen 3D
>> >>> solvers produce sNp files & TDR type simulations, but the reference
>> planes were always muted. Are these solvers capable of producing a sNp
>> file that would include the non-GND plane as one of the ports? What meaning
>> would it have, since this plane is clearly not 50ohm?
>> >>> 3. Is the noise on the power
>> >>> planes more dangerous than noise on the GND planes? (Isnt that one
>> >>> of the main reasons we have the signal routed as a differential pair)
>> >>>
>> >>> Thanks,
>> >>> Shchif
>> >>>
>> >>> ________________________________
>> >>> From: Scott McMorrow <scott@xxxxxxxxxxxxx>
>> >>> To: shchifwork@xxxxxxxxx
>> >>> Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
>> >>> Sent: Thursday, January 10, 2013 3:45 PM
>> >>> Subject: Re: [SI-LIST] Reference layers for high speed diff pairs
>> >>>
>> >>>
>> >>> Ilan
>> >>>
>> >>> Having modeled, analyzed, designed, measured, and correlated
>> measurements to modeling for 16 and 25G packages, you most definitely want
>> to use GND/GND referencing. In fact, the entire stackup should be
>> encapsulated by Gnd layers above and below any power layers, so that the
>> first and last thing that a signal via sees is a ground layer. Otherwise,
>> noise injection into the power supplies and crosstalk peaking will occur at
>> very inconvenient places that are not necessarily localized.
>> >>>
>> >>> Unless you want to do the 3D package analysis necessary to convince
>> yourself that you might be able to use GND/Power referencing, don't do it.
>> >>>
>> >>> When it comes to the signal path in packages, ground layers, ground
>> vias, and ground balls, are good ... and power layers, power vias, and
>> power balls are bad.
>> >>>
>> >>> best regards,
>> >>>
>> >>> Scott
>> >>>
>> >>> --
>> >>>
>> >>> Scott McMorrow
>> >>> Teraspeed Consulting Group LLC
>> >>> 16 Stormy Brook Road
>> >>> Falmouth, ME 04105
>> >>> (401) 284-1827 Business
>> >>> http://www.teraspeed.com/
>> >>>
>> >>> Teraspeed® is the registered service mark of Teraspeed Consulting
>> >>> Group LLC
>> >>>
>> >>> On Thu, Jan 10, 2013 at 5:56 AM, Ilan Wolff <shchifwork@xxxxxxxxx>
>> wrote:
>> >>>
>> >>> Hi experts,
>> >>>> I'm workingon a package design. This chip will have multiple 10G
>> (and up) differential pairs running between the PCB balls & the silicon
>> bumps.
>> >>>> We are able (in terms of ball-out, bump-out & package layer count)
>> to accommodate the following 2 configurations:
>> >>>> 1.Sandwiching the diff pairs between 2 GND (Analog Vss) layers.
>> >>>> 2. Sandwiching the diff pairs between1 GND (Analog Vss) layer& 1
>> SERDES supply layer (Tx supply for Tx pairs & Rx supply for Rx pairs).
>> >>>>
>> >>>>
>> >>>> Additional information:
>> >>>> Both non-GND supplies will have AC decoupling caps underneath the
>> chip, on the PCB, near the supply's vias into the package.
>> >>>> If using option 2, on the PCB end of the package, each diff pair
>> will have two reference viasof the relevant non-GND supply & (at least) two
>> reference viasof GND.
>> >>>>
>> >>>> looking at our past designs we have packages using both options.All
>> of them seem to work well. But now that we're moving on in data rates I'd
>> like to make an informative decision.
>> >>>> I'm trying to figure out if there is any preference in terms of SI.
>> >>>>
>> >>>> Care to voice your opinion?
>> >>>>
>> >>>> Many thanks,
>> >>>> Shchif
>> >>>>
>> >>>>
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>
>
> --
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 16 Stormy Brook Road
> Falmouth, ME 04105
>
> (401) 284-1827 Business
>
> http://www.teraspeed.com
>
> Teraspeed® is the registered service mark of
> Teraspeed Consulting Group LLC
>
>
>
>
>
--
Scott McMorrow
Teraspeed Consulting Group LLC
16 Stormy Brook Road
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
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